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Awards Committee

  • Awards Committee Chair

    • Samar K. Saha
       - Senior Member
      Samar K. Saha portrait
      Prospicient Devices
      Milpitas, CA 95035
      USA
      Phone 1:
      +1 408 966 5805

      Phone 2
      408-966-5805

      Lecture Topics: (1) Compact Variability Modeling; (2) Scaling Flash Memory Cell to Nanometer Regime; (3) High-performance and Ultra-low Power CMOS Device and Technology

  • Awards Committee Members

    • Narain Arora
      Narain Arora portrait placeholder
      SilTerra USA, Inc.
      1740 Technology Drive, Suite 530
      San Jose, CA 95110
      USA

      Lecture Topics:


      1) GPU based parasitic capacitance extractor for VLSI design
      2) Modeling and characterization of VLSI interconnects

    • Constantin Bulucea
       - Life Fellow
      Constantin Bulucea portrait
      Distinguished Member of the Technical Staff
      Texas Instruments, Retired
      1374 Arleen Avenue
      Sunnyvale, CA 94087
      USA
      Land:
      +1 408 738 9035

      Cell:
      +1 408 508 8120

      Constantin Bulucea (S'69–M'70–SM'88–F'04- LF'13) was born in Romania, where he received the M.S. and Ph.D. degrees in Electronics from thePolytechnic Institute of Bucharest in 1962 and 1974, respectively. In 1969, hewas granted a one-year government scholarship at the University of California, Berkeley,where he received a M.S. degree in Electrical Engineering. His activeprofessional career spanned 50 years, equally split across the Romanian and USsemiconductor histories.


      In Romania, Dr. Bulucea was the scientific director anddirector of the R&D Institute for Electronic Components (ICCE) between 1974and 1986, with assignments of national importance, such as the introduction ofsilicon transistor technology and the development of the process technology forthe Microelectronica MOS/VLSI plant. From that period, his personal legacy includes the creation of theAnnual Conference for Semiconductors (CAS), now an international IEEE event, agraduate course and a book on Linear Integrated Circuits and reference paperson surface breakdown and hot-carrier injection in silicon, originallycommunicated at IEDM and later published in the IEEE Transactions on ElectronDevices and Solid-State Electronics.


      In the US, Dr. Bulucea remained on the technical side of thesemiconductors business, so enjoying the last years of Silicon Valley's "HappyScaling". In particular, at NationalSemiconductor, he was the architect of company's 0.25, 0.18, and 0.13 µm CMOSprocesses for analog and mixed-signal applications. Before that, he brought to completionSiliconix's device/process architecture for the next generation of trench powerDMOS transistors, which became an industry standard in the followingyears. He has been active on the R&Darena as a direct contributor and also as the 2003 chairman of the Advanced Devicesand Technologies thrust of the Semiconductor Research Corporation (SRC) and asa member of the Technical Committees of the Bipolar Circuits and TechnologyMeeting (BCTM) and of the VLSI Technology Symposium. Between 2004 and 2012 hewas the editor of IEEE Electron Device Letters (EDL) for analog andmixed-signals technology. Dr. Bulucea has published over 50 technical articlesin international journals and holds 67 US patents with several others pending.


      In 2001 Dr. Bulucea was elected an Honorary Member of theRomanian Academy and in 2004 became an IEEE Fellow "for contributions totransistor engineering in the area pf power electronics". In 2011, he became aDistinguished Member of the Technical Staff of Texas Instruments (TI), as aresult of TI's acquisition of National Semiconductor. Dr. Bulucea retired from TI next year, on his72nd birthday, continuing to support company's patent applications that he had authored.


      Lecture Topics:


      1. “Physics and Technology of Sub-0.25-mm CMOS Devices” (UC Davis Seminar, 2001).


      2. “Electronic Properties of Silicon and other <Known Materials>” (Stanford Center for Integrated Research, 2003).


      3. “TCAD Revisited – An Engineer’s Point of View” – Excellence in Computer Simulation Symposium of the Network for Computational Nanotechnology (UC Berkeley, 2007).


      4. “Devices and Processes for Mixed Signals” (UC San Diego Seminar, 2003 and 2010). 


      5. Eastern Europe’s Semiconductor Technology - Recollections and Projections (Keynote Address, ESSDERC/ESSCIRC, Bucharest 2013).

    • Joachim N. Burghartz
      Joachim N. Burghartz portrait
      Institute for Microelectronics Stuttgart (IMS CHIPS)
      Director and Chairman of the Board
      StuttgartGermany
      Phone 1:
      +49 0 711 21855 200

      Fax:
      +49 0 711 21855 222
      Lecture Topics: Ultra-Thin Chips – A New Paradigm in Silicon Technology; High-Dynamic Range CMOS Imagers and Their Applications
    • Simon Deleonibus
       - Fellow
      Simon  Deleonibus portrait placeholder
      Chief Scientist/Directeur Scientifique
      Silicon Technologies
      CEA/LETI, MINATEC
      17 rue des Martyrs
      Grenoble Cedex 38054
      France
      Phone 1:
      +33 438 785973

      Fax:
      33 438 785183
      Lecture Topics: Nanoelectronics CMOS and Memories Integration and Scaling, Hetrogeneous Integration of Devices and Materials, M/NEMS, 3D integration, Bonding and Integration, More Moore, More than Moore, Beyond CMOS devices
    • Subramanian Iyer
       - Fellow
      Subramanian Iyer portrait placeholder
      Distinguished Chancellors Professor and IBM Fellow
      Electrical Engineering Department
      UCLA
      CA 90024
      USA
      Work:
      310 825 6913

      Cell:
      914 329 3341

      Lecture Topics: Orthogonal Scaling, embededed Memory, system scaling, 3D integration, semiconductors
    • Meyya Meyyappan
       - Fellow
      Meyya  Meyyappan  portrait
      NASA Ames Research Center
      Center for Nanotechnology
      Mailstop 229-3
      Moffett Field, CA 94035
      USA
      Phone 1:
      +1 650 604 2616

      Fax:
      +1 650 604 5244
      Lecture Topics: 1. An overview of recent developments in Nanotechnology

      2. Nanotechnology in nanoelectroncis, optoelectronics and sensor development

      3. Carbon based electronics

      4. Nanotechnology: development of practical systems and nano-micro-macro integration.
    • Durga Misra
       - Senior Member
      Durga  Misra portrait placeholder
      NJ Institute of Technology
      Electrical and Comp. Eng. Department
      323 M L King Blvd.
      Newark, NJ 07102-1824
      USA
      Phone 1:
      +1 973 596 5739

      Lecture Topics:
      1. Challenges for Nanoelectronics: More Moore and More than Moore.
      2. High-k on High-Mobility Substrates: An interface Issue
    • Hisayo S. Momose
       - Fellow
      Hisayo S.  Momose portrait placeholder
      Yokohama National University
      79-5 Tokiwadai, Hodogaya-ku
      Yokohama 240-8501
      Japan
      Phone 1:
      +81 45 339 3213

      Fax:
      +81 45 339 4456
    • Richard S. Muller
       - Professor in the Graduate School, Professor Emeritus Elec. Engr. and Computer Sciences Dept.
      Richard S. Muller portrait
      University of California, Berkeley
      568 Cory Hall, MS 1770
      Berkeley, CA 94720-1770
      USA
      Muller Office:
      +1 510 643 0614

      Assistant Dalene Schwartz Corey:
      +1 510 643 6690

      Fax:
      +1 510 643 6637
      Muller Email:
      muller@berkeley.edu

      Assistant Email:
      dalene@berkeley.edu
      Research Areas: Microdynamic systems, techniques, fabrication methods, and materials for MEMS and NEMS. Micro-optics and micro-optical systems

      Professional Memberships: Life Fellow IEEE, Secretary, Transducer Research Foundation, Liaison Officer—National Academy of Engineering and National Research Council

      Biography: Mechanical Engineer, Stevens Institute of Technology (1955), PhD Electrical Engineering and Physics, California Institute of Technology (1962), Professor in Electrical Engineering and Computer Sciences, University of California, Berkeley (1962–1994), Professor Emeritus and Professor in the Graduate School, Univ. of California, Berkeley (1994-present). Co-Founder (with R.M.White) Berkeley Sensor & Actuator Center (1986). Editor-in-Chief, IEEE/ASME Journal of MEMS (1997-2012). Elected to National Academy of Engineering (1994), IEEE Cledo Brunetti Award (1998 with R.T. Howe), IEEE/Wolfson Royal Society of Edinburgh James Clerk Maxwell Award (with R.M. White, 2013), IEEE MEMS Career Award (1997). Trustee, Stevens Institute of Technology (1995–2005). Fulbright Professor at TU Munich (1982-83), Alexander von Humboldt Professor at TU Berlin (1994-95). General Chair: IEEE MEMS Research Workshop (1988); General Chair: IEEE Transducer Research Conference (1991).
    • Yuan Taur
      Yuan Taur portrait placeholder
      University of California, San Diego
      Dept. of Electrical and Computer Eng.
      Mail Code 0407
      La Jolla, CA 92093-0407
      USA
      Phone 1:
      +1 858 534 3816

      Fax:
      +1 858 822 1247
    • Ravi M. Todi
       - MOS Devices and Technology
      Ravi M.  Todi portrait
      Fellow
      Director, Product Management
      GlobalFoundries
      2600 Great America Way
      Santa Clara, CA 95054
      USA
      Phone 1:
      408-462-4926

      Ravi Todi received his M.S. degree in Electrical and Mechanical Engineering from University of Central Florida in 2004 and 2005 respectively, and his doctoral degree in Electrical Engineering in 2007. His graduate research work was focused on gate stack engineering, with emphasis on binary metal alloys as gate electrode and on high mobility Ge channel devices. In 2007 he started working as Advisory Engineer/Scientist at Semiconductor Research and Development Center at IBM Microelectronics Division focusing on high performance eDRAM integration on 45nm SOI logic platform. Starting in 2010 Ravi was appointed the lead Engineer for 22nm SOI eDRAM development. For his many contributions to the success of eDRAM program at IBM, Ravi was awarded IBM’s Outstanding Technical Achievement Award in 2011. Ravi Joined Qualcomm in 2012, responsible for 20nm technology and product development as part of Qualcomm’s foundry engineering team. Ravi is also responsible for early learning on 16/14 nm FinFet technology nodes. Ravi had authored or co-authored over 50 publications, has several issues US patents and over 25 pending disclosures.