Educational Activities Committee

  • Education Committee Chair

    • Mansun J. Chan
      Mansun J.  Chan portrait
      Hong Kong University of Science and Tech.
      Dept. of Electronic and Computer Eng.
      Clear Water Bay, Kowloon, Hong Kong
      Phone 1:
      +852 2358 8519

      +852 2358 1485
      Email 1:

      Lecture Topics:  1) Nano-device physics and technology 2) Device modelling and circuit simulation 3) Non-volatile memory technology 4) Bio-sensors and circuits MANSUN CHAN received his MS and Ph.D. from the University of California at Berkeley. He is currently a Professor at the Department of Electronic and Computer Engineering of the Hong Kong University of Science and Technology (HKUST). His main research covers novel silicon device fabrication and modeling. In particular, he is one of the key developers of the BSIM model series that have been selected to be the industrial standard models for conventional and SOI MOSFETs used by the semiconductor industry worldwide. Prof. Chan has served IEEE in various capacities and he is currently a Distinguished Lecturer of IEEE EDS.

      Biography:  Mansun Chan (S’92-M’95-SM’01-F’13) received Ph.D. degrees from the UC, Berkeley in 1995. He is one of the major contributors to the unified BSIM model for SPICE, which has been accepted by most US companies and the Compact Model Council (CMC) as the first industrial standard MOSFET model. In January 1996, he has joined the EEE faculty at Hong Kong University of Science and Technology.  After that, he developed a SOI MOSFET model, which has been adopted by UC Berkeley as the core of the BSIMSOI model.  Between July 2001 and December 2002, he was a Visiting Professor at University of California at Berkeley and the Co-director of the BSIM program.  In this capacity, he has successfully completed the technology transfer of BSIM3SOI to be the first industrial standard SOI MOSFET model.  In addition to device modeling, Prof. Chan’s current research interests also include nano-transistor fabrication technology, carbon-based device physics, printable transistors, 3D integrated circuits, bio-sensors and cloud computing based simulation platform.  He is current working on an interactive modeling and online simulation (i-MOS) platform to facilitate the interactions between model developers and circuit designers using the Internet technology.

      Prof. Chan is a recipient of the UC Regents Fellowship, Golden Keys Scholarship for Academic Excellence, SRC Inventor Recognition Award, Rockwell Research Fellowship, R&D 100 award (for the BSIM3v3 project), Teaching Excellence Appreciation award, Distinguished Teaching Award and the Shenzhen City Technology Innovation Award by the Chinese Government. He is a Fellow and Distinguished Lecturer of IEEE.

  • Education Committee Members

    • Daniel Mauricio Camacho Montejo
      Daniel Mauricio  Camacho Montejo portrait placeholder
      Intel Corporation
      Folsom Design Center
      Folsom, CAUSA
    • Steve S. Chung
       - Fellow
      Steve S.  Chung portrait
      National Chiao Tung University
      Dept. of Electronics Engineering
      1001 University Road
      Hsinchu 300
      Phone 1:
      +886 3 5731830

      +886 3 5734608

      Lecture Topics:  1. The Variability Issues of Small Scale CMOS Devices 2. Extension of Moore's Law Via Strained Technologies 3. Fundamentals of RTN and Its applications to CMOS and Nonvolatile Memories 4. Random Dopant Variations of Trigate CMOS Devices

      Biography:  STEVE S. CHUNG (S'83-M'85-SM'95-F'06) received his Ph.D. degree from the University of Illinois at Urbana-Champaign, in Electrical Engineering in 1985. His Ph.D. thesis advisor is the world-famous scholar and CMOS Co-Inventor, Prof. C. T. Sah.

      Currently, he is a Chair Professor and UMC Research Chair Professor at the National Chiao Tung University (NCTU).  After joining NCTU in 1987, he has been the first Department Head of EECS Honors Program, to promote an undergraduate program for academic excellence from 2004-2005. Later, he was also the Dean of International Affairs Office, Executive Director of school level research center, between 2007-2008. He was a Research Visiting Scholar with Stanford University in 2001, visiting professor to University of California-Merced in 2009-2010, and a guest lecturer at Stanford in the Fall of 2009. He was also the consultant to the two world largest IC foundries, TSMC and UMC, on developing CMOS and flash memory technologies. His recent current research areas include- nanoscale CMOS devices and technology; nonvolatile memory technology and reliability; and reliability physics/interface characterization. He has published more than 220 journal and conference papers, one textbook, and holds more than 20 patents. Since 1995, he has presented more than 22 times in the IEEE flagship conferences, IEDM and VLSI. In particular, he was the first (from Taiwan) to present the paper at VLSI Technology symposium in 1995.

      He is an IEEE Fellow, the current IEEE EDS BoG(Board of Governor) member, IEEE Distinguished Lecturer, EDS Regions/Chapters Chair, and with past involvement as EDS AdCom member (2004-2009), EDS Regions/Chapters Vice-Chair, Guest Editor of TDMR, and Editor of EDL(2002-2008). He has served on various IEEE conference committees, e.g., VLSI Technology, IEDM, IRPS, IPFA, ICMTS, SNW, VLSI-TSA etc. Also, he has served as the TPC Vice-Chair and subsequently the organizing member of SSDM in Japan. ED Taipei chapter was awarded the 2002 EDS Chapter of the Year Award under his leadership as the chapter chair. He was awarded 3 times outstanding Research Award, distinguished PI, and distinguished NSC Research Fellow, from the National Science Council, as well as Distinguished EE Professor and Engineering Professor of the Engineering Societies in Taiwan. More recently, he was also honored the recipient of 2013 Pan Wen Yuan award in recognizing his outstanding achievements in the semiconductor research.

    • Carmen M. Lilley
      Carmen M. Lilley portrait
      University of Illinois at Chicago
      Department of Mechanical Engineering
      1200 West Harrison St.
      3031 ERF MC 251
      Chicago, Illinois 60607
      Phone 1:


      Dr. Carmen M. Lilley obtained her BS in General Engineering at the University of Illinois at Urbana-Champaign in 1998. She then attended Northwestern University and obtained her PhD in Theoretical and Applied Mechanics in 2003. Upon completing her PhD, she joined the Department of Mechanical and Industrial Engineering at the University of Illinois at Chicago as an Assistant Professor and was promoted to Associate Professor in 2010. Dr. Lilley has published in prestigious journals such as the Applied Physics Letters (APL), Journal of Applied Physics (JAP), and Nano Letters. She served as an Associate Editor for the ASME Journal of Computational on Nonlinear Dynamics from 2011-2015, and has reviewed manuscripts for APL, Journal of Applied Mechanics, JAP, Journal of Vibration and Acoustics, and Nano Letters. She has received various awards such as the National Science Foundation Faculty Early Career (CAREER) Development Award and the College of Engineering Research Award.
      Dr. Lilley is a senior member of IEEE. Within EDS, Dr. Lilley is on the IEEE Electron Devices Society Educational Committee Member (2012-Present), Chair of the MS and PhD Fellowship Committee (2014-Present), and a Board-of-Governors Member-at-Large (2015-Present). She is the technical committee chair on Nanomaterials for the Nanotechnology Council (NTC) (2006-Present) and served as their Council Representative for IEEE Women in Engineering Society (2012-2016). She has also served on the program committee for the NTC flagship conference IEEE Nano as a reviewer, track chair, and was the technical program chair for IEEE Nano 2014.
    • Ming Liu
       - Senior Member
      Ming Liu portrait
      Director - Lab of Nano-fabrication and Novel Device Integration Technology
      Institute of Microelectronics, CAS
      No.3, Bei-Tu-Cheng West Road
      Beijing 100029
      Phone 1:

      Lecture Topics: nano-fabrication, advanced memory device (charge trap memory, nanocrystal floating gate and resistive switching memory device), nano-electronic device and integrated technology, molecular electronic device and its integration
    • Chandan Sarkar
      Chandan Sarkar portrait placeholder
      Jadavpur University
      Dept. of Electronics and Telecomm. Eng.
      Kolkata 700032
      Phone 1:
      +91 94 3380 8582

      +91 33 2414 6217
      Lecture Topics: Advance CMOS FOR Analog and RF application CMOS based Memory devices
    • Mani Vaidyanathan
      Mani Vaidyanathan portrait placeholder
      University of Alberta
    • Anping Zhang
      Anping Zhang portrait placeholder
      School of Electronic Engineering
      Xian Jiaotong University
      No. 28 Xianning W Road
      Xi'an 710049