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From Deep Trenches to Skyscrapers-- Orthogonal Scaling Abstract

The absence of cost effective lithography and patterning schemes is predicted to make the historical expectations of the cost –performance benefits of scaling (popularly known as Moore’s "Law") difficult to sustain. In this talk we introduce the concept of orthogonal scaling. Orthogonal scaling refers to features that can be added to the technology which significantly enhance the technology and which are sustainable over several generations of technology.

We will examine three such orthogonal features that have either been implemented or are being actively worked on. The first is embedded memory, where the integration of logic based embedded DRAMs can effectively yield up to a generational jump in effective density. The second case we will consider is the use of deep trench decoupling that can reduce mid-frequency power supply noise in processor and general purpose ASICs effectively adding up to 10% in chip performance above the scaling entitlement.  Finally, we will examine how three dimensional integration which, depending on its implementation, can address die size, performance, process simplicity and cost beyond the 
expectation of semiconductor scaling.

We summarize this talk with where the fundamental limits are and what our long-term options are.