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Parasitic Inductance Hindering Utilization of Power Devices Abstract

Parasitic inductance (LS) in commutation circuits not only generates overvoltage but also changes switching characteristics of bipolar devices. The current waveforms during turn-off become sharper under high LS and excessive tail charge has to be design into the devices to maintain soft switching. As an example, a 750V IGBT is discussed. Due to LS in the inverter, a version had to be chosen, which has more tail current and results in higher switching losses. 

Inverters for motor drives have to withstand overload conditions. Parasitic inductance becomes most effective under these overloads. If gate drive resistors are chosen for these overload conditions it leads to twice the switching losses for normal operation.

During turn-off, the di/dt of trench-field-stop IGBTs first rises with rising gate resistance, reaches a peak of di/dt at a certain gate resistance and then falls with further rise in gate resistance. If LS is too high, gate resistance cannot be cho-sen to lie in the first range of moderate di/dt. Then, the gate resistance has become very high resulting in an unintended slow voltage rise and high turn-off losses.

For paralleled power devices, especially controlled devices, small parasitic inductance can have a big impact on current sharing. If inductive voltage drop affects the gate voltage, less than one Volt may result in large imbalance of current during turn-on. Half-bridges which contain paralleled power devices should receive their load current out of a direction, which is perpendicular to the direction of paralleling inside the modules. Otherwise small parasitic inductance deterio-rates the gate voltages inside the modules. Half-bridges within an inverter should be oriented to have all load currents perpendicular to the direction of paralleling, inside. This ensures current sharing within paralleled power devices.

Dr. Reinhold Bayerer
Infineon Technologies AG, Germany