Daewon Ha

Silicon and Column IV Semiconductor Devices
Memory Devices and Technology

Samsung Electronics Co Ltd
New Memory Lab Semiconductor R & D Center San 16 Banwol-Dong Hwasung-City
Gyeonggi-do 445-701
Phone: 82 31 208 0699
    Fax: 82 31 209 4493

Daewon Ha received the B.S. and M.S. degrees in electrical engineering from Yonsei University, Seoul, Korea, in 1993 and 1995, respectively, and the Ph.D. degree in electrical engineering and computer science from University of California, Berkeley, USA in 2004.

In 1995, he joined Samsung Electronics, Co., Ltd., Korea where he was involved in the development of world-first fully working 1 Gb and 512 Mb dynamic random access memory (DRAM) as a process integration engineer. From 2000 to 2004, he conducted research in the field of nano-scale CMOS devices using advanced transistor structures and materials such as ultra-thin silicon body single- and double-gated MOSFET (UTBFET and FinFET). In 2004, he re-joined Samsung Electronics, Co., Ltd., and has been involved in the development of 1 Gb DRAM using 68 nm technology and 64 Mb, 512 Mb, 1 Gb, and 8 Gb phase change random access memory (PRAM). He has published more than 50 technical papers and holds more than 30 issued and pending patents on memory technology. His current research interests are nano-scale CMOS devices, emerging memory technologies and reliability such as phase-change memory and resistive memory, and so on.

Dr. Ha was a recipient of Best Paper Award from European Solid-State Device Research Conference (ESSDERC) in 1999, and Samsung Best Paper Award (Gold Prize) in 2005. He served as a sub-committee member of the International Electron Devices Meeting (IEDM) from 2010 to 2011, and the International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) from 2008 to 2010.