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Regions/Chapters Committee

  • Vice President of Regions & Chapters

    • M.K. Radhakrishnan
       - Senior Member
      NanoRel Technical Consultants
      273, 18D Main, 6th Block
      Koramangla, Bangalore 560095
      India
      Phone 1:
      +91 80 25630695

      Phone 2
      +91 9447663869

      Lecture Topics: 1. Physical Analysis Challenges and Interface Physics Studies in Silicon Nano Devices 2.  Building in Reliability in Devices through Analysis and Study of Failure Mechanisms.


      Biography:  M.K. Radhakrishnan (M’82-SM’94) received B.Sc from Kerala University, India in 1972, M.Sc in Solid State electronics from Sardar Patel University, India in 1975 and Ph.Ddegree in Semiconductor Physics from Cochin University of Science and Technology in 1981.


      He is currently Directorof NanoRel Technical Consultants Singapore from 2004.  He has been with Indian Space Research Organization till 1990. From 1991-1993 he was with ST Microelectronics Singapore. From 1993 to 2001 he was with Institute of Microelectronics Singapore, where he pioneered the setting up of a full-fledged device failure analysis laboratory.  From 1994 to 2004 he served as adjunct professor at National University of Singapore. His current research interests include analysis and reliability in nano-electronic devices and interface physics studies.


      Dr. Radhakrishnan is a fellow of Institution of Electrical and Telecommunication Engineers India, member of Electron Device Failure Analysis Society (EDFAS) USA and ESD Association USA.  He served as Editor of Journal of Semiconductor Technology and Science (Korea) during 2001-2003 and is an Editorial board member of Microelectronics Reliability journal (UK). He served as Guest Editor to IEEE Transactions Devices Materials and Reliability and edited or co-edited of 4 conference proceedings.  He was Technical Chair IEEE International Symposium on Physical and Failure Analysis of ICs (IPFA) in 1995 and 1997 and General Chair of IPFA in 1999.  He was IEEEIEDST General Chair in 2009. He has been in the technical program committees of ESREF, IRPS, EPTC, MIEL, ICEE and EOS/ESD Symposium.  Currently he is the Editor-in Chief of IEEE EDS Newsletter and serves as a member of IEEE EDS Technical Committee on Electronic Materials.  He is a Distinguished Lecturer of IEEE Electron Devices Society.


       

  • Regions & Chapters Committee Members

    • Chih-Hung (James) Chen
      McMaster University
      Associate Professor, Electrical and Computer Engineering
      ITB-A321 McMaster University
      1280 Main Street West
      Hamilton, Ontario L8S 4K1
      Canada
      Phone 1:
      +1 905 525 9140 Ext. 27084

      Fax:
      +1 905 521 2922
    • Albert Chin
       - Fellow
      Thin Film Transistors
      National Chiao Tung University
      Dept. of Electronics Engineering
      Hsinchu Taiwan
      Phone 1:
      +886-3573-1841

      Fax:
      +886-3572-4361
      Lecture Topics: high-Îș Si and Ge CMOS, high-Îș flash memory, ultra-low power green electronic devices, TFT, device-level 3D IC, Si RF devices

      Biography: Albert Chin received Ph.D. from University of Michigan, Ann Arbor, in 1989 and B.S. from National Tsing Hua University in 1982.
      He was with AT&T Bell Labs, General Electric E-Lab, and Texas Instruments SPDC. He has been a professor, vice executive officer of diamond project and deputy director of National Chiao Tung University, and a visiting Professor at National University of Singapore.
      He is a pioneer on low DC-power high-Îș CMOS, high-Îș Flash memory, high mobility Ge-On-Insulator, low AC-power 3D IC, high power asymmetric-MOSFET, Si fs/THz devices, and resonant-cavity photo-detector. He co-authored >500 papers and 7 “Highly Cited Papers” (top 1% citation). His high-Îș CMOS, GeOI, Flash memory, and RF devices were also cited by ITRS www.itrs.net
      Dr. Chin has served as Subcommittee Chair and Asian Arrangements Chair of IEDM Executive Committee, Editor of IEEE Electron Device Letters, Guest Editor & Editor-in-Chief of IEEE JEDS Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices, and IEEE EDS Technical Committee Chairs on both Electronic Materials and Compound Semiconductor Devices & Circuits. He is an IEEE Fellow, Optical Society of America Fellow, and Asia-Pacific Academy of Materials Academician.
    • Ming Liu
       - Senior Member
      Director - Lab of Nano-fabrication and Novel Device Integration Technology
      Institute of Microelectronics, CAS
      No.3, Bei-Tu-Cheng West Road
      Beijing 100029
      China
      Phone 1:
      86-10-82995578

      Fax:
      86-10-82995583
      Lecture Topics: nano-fabrication, advanced memory device (charge trap memory, nanocrystal floating gate and resistive switching memory device), nano-electronic device and integrated technology, molecular electronic device and its integration
    • Durga Misra
       - Senior Member
      NJ Institute of Technology
      Electrical and Comp. Eng. Department
      323 M L King Blvd.
      Newark, NJ 07102-1824
      USA
      Phone 1:
      +1 973 596 5739

      Lecture Topics:
      1. Challenges for Nanoelectronics: More Moore and More than Moore.
      2. High-k on High-Mobility Substrates: An interface Issue
    • Adelmo Ortiz-Conde
       - Senior Member
      Silicon and Column IV Semiconductor Devices; Thin Film Transistors
      Universidad Simon Bolivar
      Dpto. de Electronica
      Apartado Postal 89000
      Caracas 1080
      Venezuela
      Phone 1:
      +58-212-9064010

      Fax:
      +58-212-9064025
      Adelmo Ortiz-Conde (S’82, M'85, SM'97) was born in Caracas, Venezuela, on November 28, 1956. He received the professional Electronics Engineer degree from Universidad Simón Bolívar (USB), Caracas, Venezuela, in 1979 and the M.E. and Ph.D. from the University of Florida, Gainesville, in 1982 and 1985, respectively. His doctoral research, under the guidance of Prof. J. G. Fossum, was on the Effects of Grain Boundaries in SOI MOSFET’s.
      From 1979 to 1980, he served as an instructor in the Electronics Department at USB. In 1985, he joined the technical Staff of Bell Laboratories, Reading, PA, where he was engaged in the development of high voltage integrated circuits. Since 1987 he returned to the Electronics Department at USB where he was promoted to Full Professor in 1995. He was on sabbatical leave at Florida International University (FIU), Miami, from September to December 1993, and at University of Central Florida (UCF), Orlando, from January to August 1994, and again from July to December 1998. He also was on sabbatical leave at “Centro de Investigaciones y Estudios Avanzados” (CINVESTAV) National Polytechnic Institute (IPN), Mexico City, Mexico, from October 2000 to February 2001.
      He has coauthored one textbook, Analysis and Design of MOSFETs: Modeling, Simulation and Parameter Extraction (2012 Springer reprint of the original 1st ed. 1998, http://dx.doi.org/10.1007/978-1-4615-5415-8 ), over 170 international technical journal and conference articles (including 18 invited review articles). His present research interests include the modeling and parameter extraction of semiconductor devices.
      Dr. Ortiz-Conde is an EDS Distinguished Lecturer and the Chair of IEEE’s CAS/ED Venezuelan Chapter. He is editor of IEEE Electron Device Letters in the area of Silicon Devices and Technology. He was the Region 9 Editor of IEEE EDS Newsletter from 2000 to 2005. He is a Member of the Editorial Advisory Board of various technical journals: Microelectronics and Reliability, “Universidad Ciencia y Tecnología” and “Revista Ingeniería UC”. He regularly serves as reviewer of several international journals and he was the General Chairperson of the first IEEE International Caribbean Conference on Devices, Circuits, and Systems (ICCDCS) in 1995, Technical Chairperson of the second, fourth and fifth editions of this conference in 1998, 2002 and 2004 respectively, and the Chairperson of the Steering Committee in 2000.

      Lecture Topics: MOSFET threshold voltage extraction methods. Compact models of Double-Gate MOSFETs. Evolution of MOSFETs toward nanoelectronics. Integration-based Methods for Device Parameter Extraction and Distortion Evaluation Modeling. Characterization of Diodes and Solar Cells. Application of Lambert Function.
    • Adam Osseiran
      Director NNTTF
      School of Engineering
      Edith Cowan University
      270 Joondalup Drive
      Joondalup, WA 6027
      Australia
      Phone 1:
      +61 (08) 6304 5752

      Fax:
      +61 (08) 6304 5811
    • Soumya Pandit
      Institute of Radio Physics and Electronics
      University of Calcutta
      India
      Phone 1:
      +919874852007

      Lecture Topics: Process Variability and Variability Resistant Device Design, Low Power VLSI Design, Temperature Analysis of Advanced MOS Transistor.


      Biography: Soumya Pandit received Ph.D. from Indian Institute of Technology, Kharagpur, India in the year 2009 and Master degree in Radio Physics and Electronics in the year 2000. Currently he is associated with the Institute of Radio Physics and Electronics, University of Calcutta as Assistant Professor. The research interest of Dr. Pandit includes device design and optimization for System-on-Chip Applications. Dr. Pandit was the Chair of ED Calcutta Chapter for the year 2014, 2015 and is the founder chapter advisor to ED University of Calcutta Student Branch Chapter.

    • Sean Rommel
      Rochester Institute of Technology
      82 Lomb Memorial Drive
      Rochester, NY 14623-5604
      USA