Newsletter Committee

  • Newsletter Committee Chair

    • Simon Deleonibus
       - Fellow
      Chief Scientist/Directeur Scientifique
      Silicon Technologies
      17 rue des Martyrs
      Grenoble Cedex 38054
      Phone 1:
      +33 438 785973

      33 438 785183
      Lecture Topics: Nanoelectronics CMOS and Memories Integration and Scaling, Hetrogeneous Integration of Devices and Materials, M/NEMS, 3D integration, Bonding and Integration, More Moore, More than Moore, Beyond CMOS devices
  • Newsletter Committee Members

    • Fernando Guarin
       - Fellow
      Global Foundries
      Lecture Topics: Reliability and scaling of CMOS, SiGe Reliability  
    • Hisayo S. Momose
       - Fellow
      Yokohama National University
      79-5 Tokiwadai, Hodogaya-ku
      Yokohama 240-8501
      Phone 1:
      +81 45 339 3213

      +81 45 339 4456
    • M.K. Radhakrishnan
       - Senior Member
      NanoRel Technical Consultants
      273, 18D Main, 6th Block
      Koramangla, Bangalore 560095
      Phone 1:
      +91 80 25630695

      Phone 2
      +91 9447663869

      Lecture Topics: 1. Physical Analysis Challenges and Interface Physics Studies in Silicon Nano Devices 2.  Building in Reliability in Devices through Analysis and Study of Failure Mechanisms.

      Biography:  M.K. Radhakrishnan (M’82-SM’94) received B.Sc from Kerala University, India in 1972, M.Sc in Solid State electronics from Sardar Patel University, India in 1975 and Ph.Ddegree in Semiconductor Physics from Cochin University of Science and Technology in 1981.

      He is currently Directorof NanoRel Technical Consultants Singapore from 2004.  He has been with Indian Space Research Organization till 1990. From 1991-1993 he was with ST Microelectronics Singapore. From 1993 to 2001 he was with Institute of Microelectronics Singapore, where he pioneered the setting up of a full-fledged device failure analysis laboratory.  From 1994 to 2004 he served as adjunct professor at National University of Singapore. His current research interests include analysis and reliability in nano-electronic devices and interface physics studies.

      Dr. Radhakrishnan is a fellow of Institution of Electrical and Telecommunication Engineers India, member of Electron Device Failure Analysis Society (EDFAS) USA and ESD Association USA.  He served as Editor of Journal of Semiconductor Technology and Science (Korea) during 2001-2003 and is an Editorial board member of Microelectronics Reliability journal (UK). He served as Guest Editor to IEEE Transactions Devices Materials and Reliability and edited or co-edited of 4 conference proceedings.  He was Technical Chair IEEE International Symposium on Physical and Failure Analysis of ICs (IPFA) in 1995 and 1997 and General Chair of IPFA in 1999.  He was IEEEIEDST General Chair in 2009. He has been in the technical program committees of ESREF, IRPS, EPTC, MIEL, ICEE and EOS/ESD Symposium.  Currently he is the Editor-in Chief of IEEE EDS Newsletter and serves as a member of IEEE EDS Technical Committee on Electronic Materials.  He is a Distinguished Lecturer of IEEE Electron Devices Society.


    • Samar K. Saha
       - Senior Member
      Prospicient Devices
      Milpitas, CA 95035
      Phone 1:
      +1 408 966 5805

      Phone 2

      Lecture Topics: (1) Compact Variability Modeling; (2) Scaling Flash Memory Cell to Nanometer Regime; (3) High-performance and Ultra-low Power CMOS Device and Technology

    • Ravi M. Todi
       - MOS Devices and Technology
      Director, Product Management
      2600 Great America Way
      Santa Clara, CA 95054
      Phone 1:

      Ravi Todi received his M.S. degree in Electrical and Mechanical Engineering from University of Central Florida in 2004 and 2005 respectively, and his doctoral degree in Electrical Engineering in 2007. His graduate research work was focused on gate stack engineering, with emphasis on binary metal alloys as gate electrode and on high mobility Ge channel devices. In 2007 he started working as Advisory Engineer/Scientist at Semiconductor Research and Development Center at IBM Microelectronics Division focusing on high performance eDRAM integration on 45nm SOI logic platform. Starting in 2010 Ravi was appointed the lead Engineer for 22nm SOI eDRAM development. For his many contributions to the success of eDRAM program at IBM, Ravi was awarded IBM’s Outstanding Technical Achievement Award in 2011. Ravi Joined Qualcomm in 2012, responsible for 20nm technology and product development as part of Qualcomm’s foundry engineering team. Ravi is also responsible for early learning on 16/14 nm FinFet technology nodes. Ravi had authored or co-authored over 50 publications, has several issues US patents and over 25 pending disclosures.
    • Albert Z.H. Wang
       - Fellow
      University of California
      Dept. of Electrical and Computer Engineering
      Office: 417 EBU2, Lab: 227 EBU2
      Riverside, CA 92521
      Phone 1:
      +1 951 827 2555

      +1 951 827 2425

      Lecture Topics:

      1. ESD-RFIC co-design techniques.
      2. Mixed-mode ESD protection circuit simulation design methodology.
      3. Above-IC ESD protection by nano technology
      4. Field-programmable ESD protection by nano technology

    • Paul K.L. Yu
       - Fellow
      University of California at San Diego
      ECE Department, MS 0407
      9500 Gilman Dr., Eng. Bldg. Unit 1, Room 3604
      La Jolla, CA 92093-0407
      Phone 1:
      +1 858 534 6180

      +1 858 534 0556
      Lecture Topics: Recent Advances in Photonic Devices for RF/Wireless, Semiconductor Wafer Bonding Technology for Device Integration

  • Newsletter Editor-in-Chief

    • Carmen M. Lilley
      University of Illinois at Chicago
      Department of Mechanical Engineering
      1200 West Harrison St.
      3031 ERF MC 251
      Chicago, Illinois 60607
      Phone 1:


      Dr. Carmen M. Lilley obtained her BS in General Engineering at the University of Illinois at Urbana-Champaign in 1998. She then attended Northwestern University and obtained her PhD in Theoretical and Applied Mechanics in 2003. Upon completing her PhD, she joined the Department of Mechanical and Industrial Engineering at the University of Illinois at Chicago as an Assistant Professor and was promoted to Associate Professor in 2010. Dr. Lilley has published in prestigious journals such as the Applied Physics Letters (APL), Journal of Applied Physics (JAP), and Nano Letters. She served as an Associate Editor for the ASME Journal of Computational on Nonlinear Dynamics from 2011-2015, and has reviewed manuscripts for APL, Journal of Applied Mechanics, JAP, Journal of Vibration and Acoustics, and Nano Letters. She has received various awards such as the National Science Foundation Faculty Early Career (CAREER) Development Award and the College of Engineering Research Award.
      Dr. Lilley is a senior member of IEEE. Within EDS, Dr. Lilley is on the IEEE Electron Devices Society Educational Committee Member (2012-Present), Chair of the MS and PhD Fellowship Committee (2014-Present), and a Board-of-Governors Member-at-Large (2015-Present). She is the technical committee chair on Nanomaterials for the Nanotechnology Council (NTC) (2006-Present) and served as their Council Representative for IEEE Women in Engineering Society (2012-2016). She has also served on the program committee for the NTC flagship conference IEEE Nano as a reviewer, track chair, and was the technical program chair for IEEE Nano 2014.

  • Regions 1, 2 & 3 - Eastern, Northeastern & Southeastern USA Regional Editor

    • Mukta Farooq
       - Fellow
      Mukta Farooq portrait
      Term 1
      6 Dartantra Drive
      Hopewell Junction, NY 12533
      Phone 1:
      845 894 0638

      Lecture Topics:  3D Technology Overview, 3D Integration and Die Stacking


      Dr. Mukta Farooq is an expert metallurgist and materials scientist, with expertise in 3 Dimensional silicon integration and packaging, die and wafer stacking for hybrid memory cube and other applications, CMOS FET back end of line structures, flip-chip/C4 technology, lead-free alloys, chip package interaction, and intellectual property.

      Mukta is a Fellow at GlobalFoundries and the technical leader for Advanced Silicon Packaging. She is also a GlobalFoundries Master Inventor with over 190 issued U.S. and international patents. She was named an IBM Lifetime Master Inventor and a member of the Academy of Technology while at IBM. She received an outstanding technical achievement award for leadership in 3D integration technology and multiple high value patent awards. She has authored several external publications, given invited talks, and taught short courses at conferences and universities.

      Mukta is an IEEE Fellow and an EDS Distinguished Lecturer. She is also Chair of the IEEE EDS Mid-Hudson Valley Chapter. Mukta received her BS from IIT Bombay, MS from Northwestern University, and PhD from Rensselaer Polytechnic Institute.


  • Regions 4 & 7 - Central USA & Canada Regional Editor

    • Michael M. Adachi
       - Assistant Professor, School of Engineering Science
      Michael M. Adachi portrait placeholder
      Simon Fraser University
      303-2373 Atkins Ave
      Port Coquitlam, BC V3C1Y7
      Dr Adachi is an Assistant Professor of the School of Engineering Science, Simon Fraser University, where he is leading a team in developing 2D material (graphene-like material) devices.

      Dr Adachi is vice-chair of the IEEE Electron Devices Society, Vancouver Chapter. He has refereed articles for a number of journals including Nanotechnology, Nano Research Letters, Optics Communications, ACS Nano, ACS Photonics, Nature Communications, Nano Research, and Journal of Vacuum Science and Technology.
  • Regions 5 & 6 - Southwestern & Western USA Regional Editor

  • Region 8 - UK, Middle East & Africa Regional Editor

    • Jonathan Terry
      Jonathan Terry portrait
      Term 2
      Institute for Integrated Systems
      School of Engineering
      University of Edinburgh
      Edinburgh EH9 3JF
      United Kingdom
      Phone 1:
      +44 (0)131 6505607

      Jonathan Terry is a Senior Member of the IEEE and the Treasurer of the Scottish Chapter of the IEEE Electron Devices Society. He is a senior research fellow at the University of Edinburgh in the Institute for Integrated Micro and Nano Systems and an honorary research fellow at Heriot-Watt University. His research centres on the development of More-than-Moore application. This is the integration of novel materials and processing techniques with standard foundry-produced CMOS technology. Jonathan also teaches within the Universityâ
  • Region 8 - Eastern Europe Regional Editor

    • Daniel Tomaszewski
      Daniel Tomaszewski portrait
      Term 2
      Instytut Technologii Elektronowej (ITE)
      Al.Lotników 32/46
      Warsaw 02-668
      Phone 1:
      +48 (22) 2793 200

      +48 (22) 2793 202
      D.Tomaszewski (M’2014) received M.Sc degree in electronics (spec. electronic technology) from Warsaw University of Technology in 1980, and Ph.D degree in electrical engineering (spec. solid-state device electronics) from Instytut Technologii Elektronowej, Warsaw in 1998.
  • Region 9 - Latin America Regional Editor

    • Joao Martino
       - Senior Member
      Joao Martino portrait
      Term 1
      University of Sao Paulo
      Laboratory of Integrated Systems
      Av. Prof. Luciano Gualberto, trav.3, n.158
      San Paulo 05508-010
      Phone 1:
      (11) 3091-5657

      Lecture Topics: 1) SOI MOSFET: Electrical Characterization and Modeling 2) Multiple-Gate Transistors: Device Physics and Characterization 3) Single Transistor Memory Cell: 1T-DRAM 4) Tunnel FET Transistors (triple-gate and nanowire structures) 5) Radiation effects on SOI devices 6) Field Effect Transistor: From MOSFET to Tunnel FET

      Joao Antonio Martino received master (1984) and PhD (1988) degrees in microelectronics from University of Sao Paulo, Brazil. He was a postdoctoral researcher in silicon-on-insulator (SOI) devices and technology in Imec, Belgium. He is currently a full professor and the head of SOI group at University of Sao Paulo. His expertise is in electrical characterization, simulation and modeling of SOI devices in wide temperature range. He is also interested in the SOI-CMOS fabrication process, multiple-gate devices (FinFET), 1T-DRAM, Tunnel-FET and radiation effects. He has authored or coauthored of more than 400 technical journal papers and conference presentation and author/editor of 5 books. He is senior member and distinguished lecturer of the IEEE Electron Device Society (EDS). He is chair of IEEE/EDS South Brazil chapter and vice-chair of SRC IEEE/EDS R9.
  • Region 10 - Australia, New Zealand & Southeast Asia Regional Editor

    • P Susthitha Menon
      P Susthitha Menon portrait
      Term 1
      Institute of Microengineering and Nanoelectronics (IMEN)
      National University of Malaysia (UKM)
      Phone 1:

      P Susthitha Menon is currently an Associate Professor at the Universiti Kebangsaan Malaysia (UKM) at Kuala Lumpur. She received her BSEE degree from (UKM) in 1998. As an Intel scholar, she worked at Intel Malaysia as a Product Engineer for mobile modules systems from 1999 to 2002. She then received her MSc and PhD (Distinction) degrees in 2005 and 2008 respectively from UKM, for the development of Si- and InGaAs-based interdigitated p-i-n photodiodes. At the University’s Institute of Micro-Engineering & Nanoelectronics (IMEN) she is specializing in the field of optoelectronics, nanophotonics, and robust engineering optimization. Susthitha is a Senior Member of IEEE. She is in the organizing team international conference ICSE by ED Malaysia Chapter for many years and is the Secretary of the IEEE Electron Devices Malaysia Chapter.
  • Region 10 - Northeast Asia Regional Editor

    • Kuniyuki Kakushima
      Kuniyuki Kakushima portrait
      Term 2
      Interdisciplinary Graduate School of Science
      Tokyo Institute of Technology
      4259 Nagatsuta
      Midori-ku, Yokohama 226-8502
      Kuniyuki Kakushima received his M.S. and Ph.D degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 2001 and 2003, respectively. He is currently an Associate Professor of Tokyo Institute of Technology and is investigating novel processes and materials for future scaled MOS devices. Dr. Kakushima is also a member of The Japan Society of Applied Physics.
  • Region 10 - East Asia Regional Editor

    • Ming Liu
       - Senior Member
      Ming Liu portrait
      Director - Lab of Nano-fabrication and Novel Device Integration Technology
      Institute of Microelectronics, CAS
      No.3, Bei-Tu-Cheng West Road
      Beijing 100029
      Phone 1:

      Lecture Topics: nano-fabrication, advanced memory device (charge trap memory, nanocrystal floating gate and resistive switching memory device), nano-electronic device and integrated technology, molecular electronic device and its integration
  • Region 10 - South Asia (India, Bangladesh & Nepal) Regional Editor

    • Manoj Saxena
      Manoj Saxena portrait
      Term 1
      Deen Dayal Upadhyaya College
      University of Delhi
      Sector 3, Dwarka
      New Delhi 110078
      Manoj Saxena is an Associate Professor in Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India. He received B.Sc. (with honors), M. Sc., and Ph.D. degrees from the University of Delhi in 1998, 2000, and 2006 respectively. He has authored or coauthored 210 technical papers in international journals and various international and national conferences. His current research interests are in the areas of analytical modeling, design, and simulation of Optically controlled MESFET/MOSFET, silicon-on-nothing, insulated-shallow-extension, grooved/concave-gate MOSFETs, cylindrical gate MOSFET and Tunnel FET. He is a reviewer to many journals including Solid State Electronics, Journal of Physics: D Applied Physics and IEEE TED and EDL. Manoj is a Senior Member of IEEE and also Member of Institute of Physics (UK), Institution of Engineering and Technology (UK), National Academy of Sciences India (NASI) and International Association of Engineers (Hong Kong). Currently, he is the Secretary of EDS Delhi Chapter. For his voluntary contribution, Manoj received the outstanding EDS Volunteer recognition from EDS Chapters in the region in 2012.

      Lecture Topics:
      Dielectric Pocket MOSFET: A Novel Device Architecture
      Embedded Insulator based Novel Nanoscaled Novel MOSFET Structures
      Tunnel Field Effect Transistor and its Application as Highly Sensitive and Fast Biosensor
      Modeling and Simulation of Tunnel Field Effect Transistor
      Dual Material Junctionless Double Gate Transistor for Analog and Digital Performance