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VLSI Technology and Circuits Committee Overview

Objective The objective of the VLSI Technology and Circuits Committee is to identify new/hot areas of interest to the Electron Devices and Solid-State Circuits communities. Based on the nature of the areas, we will recommend any or all of the following:
  1. Initiate topical workshops of current interest (attached to existing conferences or start new ones)
  2. Special Issues for major publications (e.g., T-ED)
  3. Panel session topics for major conferences
  4. Special Sessions for major conferences
Membership This is a non-voting Ex-Officio Forum member position with a two-year renewable term. We expect to limit the membership of the committee to no more than two terms so that new ideas can be generated, incorporated, and executed.
Operation This committee operates entirely by email. There are two Society BoG meetings a year, with one meeting always being held in conjunction with IEDM. The other BoG meeting is normally held sometime in the April-June time period in conjunction with another EDS sponsored conference. 
History The VLSI Technology and Circuits Technical Committee was formed in 1998 under the leadership of Prof. Charles G. Sodini (MIT), followed by Dr. H.-S. Philip Wong (IBM), Werner Weber (Infineon), Dr. James A. Hutchby (SRC) and Dr. Bin Zhao (Freescale Semiconductor). Since its formation, the VLSI Committee has chartered its missions to identify new technical trends, to help foster new technical concepts, and to serve the emerging needs of the Electron Devices and Solid-State Circuits communities in VLSI. The committee members include many well recognized technical experts representing a very wide spectrum of technical expertise in VLSI devices, technology, and circuits. Every year, the committee brainstorms (by email) on ideas that are suitable for a new workshop, special issue for a journal, panel sessions, and special sessions for conferences. Committee members then take these ideas forward and find a way to make them happen, either by being the organizers themselves, or by finding suitable organizers for the topic. We work closely together with journal editors and conference organizers. Especially in the case of new workshops, it is much easier to attach the new workshop to existing conferences rather than to start new.
Contact If you have ideas for a new workshop, a special issue for journals, or topics for panel sessions and special sessions for conferences, please contact current committee members. If you would like to volunteer in the committee or have suggestions and comments to the activities of this committee, please contact Shuji Ikeda.

Chair:
Shu Ikeda
tei Solutions Inc.
Shinjuku Park Tower N30F
3-7-1 Nishi-Shinjuku, Shinjuku, 
Tokyo, 163-1030 Japan
+81-35326-3635 Office tel
+81-35326-3001 Office FAX
+81-80-3586-6412 Cell
shu.ikeda@tei-solutions.com
www.tei-solutions.com

 

Any comments, ideas, and suggestions related to the field of VLSI Technology and Circuits are sincerely welcome!

  • Please click here to view the committee's article from the October 2014 edition of the EDS Newsletter.
  • The EDS VLSI Committee met in December 2014 in conjunction with the EDS Board of Governors meeting series and the International Electron Devices Meeting (IEDM). 
    VLSI Committee Meeting Minutes - December 2014

 

  • VLSI Technology and Circuits Committee Chair

    • Shuji Ikeda
      Tei Solutions, Co. Ltd.
      NIRC
      16-1 Onogawa
      Tsukuba, Ibaraki 305-8
      Japan
      Phone 1:
      +81 29 849 1276

      Fax:
      +81 29 849 1533

      Shuji Ikeda (M’91-SM’02-F’04) received the B.S. degree in Physics, PhD. in Electrical Engineering from Tokyo Institute of Technology, Tokyo, Japan in 1978 and 2003 respectively and the M.S. degree in Electrical Engineering from Princeton University, Princeton, New Jersey, USA in 1987. He joined Semiconductor and Integrated Circuit Group, Hitachi ltd., Tokyo, Japan in 1978, where he was engaged in research and development of state of the art SRAM process and devices. He was also working on developing process technology for LOGIC, embedded memories, and CMOS power RF devices and on transferring technology to mass production line. He invented some of the outstanding structures for SRAM. He pioneered process to implement new materials in mass production, including W-polycide, Al-Cu-Si in 1984 and in-situ phosphorus-doped-polysilicon in 1990. He is the first to realize Lightly Doped Drain (LDD) in production to suppress Hot Carrier Injection in 1984. He also firstly implemented polyimide coat of the chip to immune SER caused by alpha particle from the resin covers the chip. In October 2000, he joined Trecenti Technologies Inc. He developed new process scheme with aggressive reduction of process time and suitable for single-wafer processing. That achieved less than 0.25days/layer cycle time. In April 2005, he joined ATDF at Austin Texas, as a Director of Technology. Where he develops various kinds of technologies includes scaled CMOS, non-classical CMOS, new materials and tools. He established tei Technology LLC in May 2008, Omni Water Solutions LLC, in 2009 at Austin Texas. He started tei Solutions Inc in Tsukuba, Ibaraki, Japan in 2010, where, he manages R&D foundry developing new devices, process technologies for VLSIs. He also integrates emerging technology onto semiconductor manufacturing technology to create innovative products/businesses. Due to his contributions to 200 MHz RISC microprocessor, he got 1999 R&D 100 Award. He served as subcommittee and executive committee member of IEDM from 1993 to 2002. He introduced Manufacturing Session in 1998 and chaired IEDM in 2002. He was a member of EDS Administrative Committee from 2005 to 2010. He was a technical program member for VLSI Technology Symposium in 2007 and 2008. He serves as a chairman of VLSI committee of EDS from 2009 and AdHoc Committee on Asia EDS Conference from 2014.

  • VLSI Technology and Circuits Committee Members

    • Reza Arghavani
      Lam Research Corp
    • Sandeep Bahl
      Texas Instruments
    • Kaustav Banerjee
      University of California
      Dept. of Elec. & Comp. Eng.
      Room 4151, Harold Frank Hill
      Santa Barbara , CA 93106-9560
      USA
      Phone 1:
      +1 805 893 3337

      Fax:
      +1 805 893 3262
      Lecture Topics: Graphene and Beyond-Graphene Nanomaterials for Green Electronics; Carbon Nanoelectronics; 2D Electronics
    • Mansun J. Chan
      Hong Kong University of Science and Tech.
      Dept. of Electronic and Computer Eng.
      Clear Water Bay, Kowloon, Hong Kong
      Phone 1:
      +852 2358 8519

      Fax:
      +852 2358 1485
      Email 1:
      mchan@ust.hk

      Lecture Topics:  1) Nano-device physics and technology 2) Device modelling and circuit simulation 3) Non-volatile memory technology 4) Bio-sensors and circuits MANSUN CHAN received his MS and Ph.D. from the University of California at Berkeley. He is currently a Professor at the Department of Electronic and Computer Engineering of the Hong Kong University of Science and Technology (HKUST). His main research covers novel silicon device fabrication and modeling. In particular, he is one of the key developers of the BSIM model series that have been selected to be the industrial standard models for conventional and SOI MOSFETs used by the semiconductor industry worldwide. Prof. Chan has served IEEE in various capacities and he is currently a Distinguished Lecturer of IEEE EDS.


      Biography:  Mansun Chan (S’92-M’95-SM’01-F’13) received Ph.D. degrees from the UC, Berkeley in 1995. He is one of the major contributors to the unified BSIM model for SPICE, which has been accepted by most US companies and the Compact Model Council (CMC) as the first industrial standard MOSFET model. In January 1996, he has joined the EEE faculty at Hong Kong University of Science and Technology.  After that, he developed a SOI MOSFET model, which has been adopted by UC Berkeley as the core of the BSIMSOI model.  Between July 2001 and December 2002, he was a Visiting Professor at University of California at Berkeley and the Co-director of the BSIM program.  In this capacity, he has successfully completed the technology transfer of BSIM3SOI to be the first industrial standard SOI MOSFET model.  In addition to device modeling, Prof. Chan’s current research interests also include nano-transistor fabrication technology, carbon-based device physics, printable transistors, 3D integrated circuits, bio-sensors and cloud computing based simulation platform.  He is current working on an interactive modeling and online simulation (i-MOS) platform to facilitate the interactions between model developers and circuit designers using the Internet technology.


      Prof. Chan is a recipient of the UC Regents Fellowship, Golden Keys Scholarship for Academic Excellence, SRC Inventor Recognition Award, Rockwell Research Fellowship, R&D 100 award (for the BSIM3v3 project), Teaching Excellence Appreciation award, Distinguished Teaching Award and the Shenzhen City Technology Innovation Award by the Chinese Government. He is a Fellow and Distinguished Lecturer of IEEE.

    • Steve S. Chung
       - Fellow
      National Chiao Tung University
      Dept. of Electronics Engineering
      1001 University Road
      Hsinchu 300
      Taiwan
      Phone 1:
      +886 3 5731830

      Fax:
      +886 3 5734608

      Lecture Topics:  1. The Variability Issues of Small Scale CMOS Devices 2. Extension of Moore's Law Via Strained Technologies 3. Fundamentals of RTN and Its applications to CMOS and Nonvolatile Memories 4. Random Dopant Variations of Trigate CMOS Devices


      Biography:  STEVE S. CHUNG (S'83-M'85-SM'95-F'06) received his Ph.D. degree from the University of Illinois at Urbana-Champaign, in Electrical Engineering in 1985. His Ph.D. thesis advisor is the world-famous scholar and CMOS Co-Inventor, Prof. C. T. Sah.


      Currently, he is a Chair Professor and UMC Research Chair Professor at the National Chiao Tung University (NCTU).  After joining NCTU in 1987, he has been the first Department Head of EECS Honors Program, to promote an undergraduate program for academic excellence from 2004-2005. Later, he was also the Dean of International Affairs Office, Executive Director of school level research center, between 2007-2008. He was a Research Visiting Scholar with Stanford University in 2001, visiting professor to University of California-Merced in 2009-2010, and a guest lecturer at Stanford in the Fall of 2009. He was also the consultant to the two world largest IC foundries, TSMC and UMC, on developing CMOS and flash memory technologies. His recent current research areas include- nanoscale CMOS devices and technology; nonvolatile memory technology and reliability; and reliability physics/interface characterization. He has published more than 220 journal and conference papers, one textbook, and holds more than 20 patents. Since 1995, he has presented more than 22 times in the IEEE flagship conferences, IEDM and VLSI. In particular, he was the first (from Taiwan) to present the paper at VLSI Technology symposium in 1995.


      He is an IEEE Fellow, the current IEEE EDS BoG(Board of Governor) member, IEEE Distinguished Lecturer, EDS Regions/Chapters Chair, and with past involvement as EDS AdCom member (2004-2009), EDS Regions/Chapters Vice-Chair, Guest Editor of TDMR, and Editor of EDL(2002-2008). He has served on various IEEE conference committees, e.g., VLSI Technology, IEDM, IRPS, IPFA, ICMTS, SNW, VLSI-TSA etc. Also, he has served as the TPC Vice-Chair and subsequently the organizing member of SSDM in Japan. ED Taipei chapter was awarded the 2002 EDS Chapter of the Year Award under his leadership as the chapter chair. He was awarded 3 times outstanding Research Award, distinguished PI, and distinguished NSC Research Fellow, from the National Science Council, as well as Distinguished EE Professor and Engineering Professor of the Engineering Societies in Taiwan. More recently, he was also honored the recipient of 2013 Pan Wen Yuan award in recognizing his outstanding achievements in the semiconductor research.

    • Simon Deleonibus
       - Fellow
      Chief Scientist/Directeur Scientifique
      Silicon Technologies
      CEA/LETI, MINATEC
      17 rue des Martyrs
      Grenoble Cedex 38054
      France
      Phone 1:
      +33 438 785973

      Fax:
      33 438 785183
      Lecture Topics: Nanoelectronics CMOS and Memories Integration and Scaling, Hetrogeneous Integration of Devices and Materials, M/NEMS, 3D integration, Bonding and Integration, More Moore, More than Moore, Beyond CMOS devices
    • Wladyslaw Grabinski
      MOS-AK Association
      CH-1291Commugny
      Station 11
      Lausanne CH-1015
      Switzerland
      Phone 1:
      41 79 883 6076

      Fax:
      +41 21 693 3640
      Lecture Topics:
      Electrical Characterization (DC, CV, RF)
      TCAD Process/Device Simulations
      SPICE/Compact Modeling
      Verilog-A Standardization
    • Ru Huang
       - MOS Devices and Technology
      Peking University
      Institute of Microelectronics
      Beijing 100871
      China
      Phone 1:
      86 10 6275 7761

      Fax:
      86 10 6275 1789 -7761
      Ru Huang (M’98–SM’06) received the B.S. (highest honors) and M.S. degrees in electronic engineering from Southeast University, Nanjing, China, in 1991 and 1994, respectively, and the Ph.D. degree in microelectronics from Peking University, Beijing, China, in 1997.
      In 1997, she joined the faculty of Peking University, where she is currently a Professor and the Head of the Department of Microelectronics. Since 2000, she has been the leader of several State Key Research Projects of China in device research and IC fabrication technology research, including major state basic research projects, 863 national projects, the key project from National Natural Science Foundation, as well as several collaborative projects with Samsung, Intel and Fujitsu Corporations. Her research interests include nano-scaled CMOS devices, nonvolatile memory devices and new devices for RF and harsh environment applications. She holds 21 granted patents, and has authored/co-authored 4 books and over 180 papers, including many conference invited papers. Dr. Huang is the winner of the National Science Fund for Distinguished Young Scholars and many other awards in China, including the National Youth Science Award, Science and Technology Progress Award from Ministry of Information Industry and Ministry of Education. She serves as a member of IEEE Electron Devices Society (EDS) AdCom and the associate chief editor of Science in China. She was the Technical Program Co-Chair of the 7th and 9th International Conference on Solid State and Integrated Circuit Technology (ICSICT 2004 and 2008), a Far East Committee Member of the 2004 International Solid State Circuits Conference (ISSCC), and committee members of many other international conferences and symposiums.
    • Kazunari Ishimaru
      Toshiba Corporation
      Japan
    • Hiroshi Iwai
       - Fellow
      Interdisciplinary Graduate School of Science and Engineering
      4259 Nagatsuta, Midori-ku
      Yokohama 226-8502
      Japan
      Phone 1:
      +81 45 924 5471

      Fax:
      +81 45 924 5584

      Lecture Topics: Future of Nano CMOS Technology

    • Seiichiro Kawamura
      JST/CRDS
      Uehara, Shibuya, TokyoJapan
      Phone 1:
      +81 3 3460 4536

      Fax:
      +81 3 3460 2031
    • Carlos Mazure
    • Gaudenzio Meneghesso
       - Compound Semiconductor Devices
      Fellow
      University of Padova
      Department of Information Engineering
      Via Gradenigo 6/B
      Padova 35131
      Italy
      Phone 1:
      +1 390498277653

      Fax:
      +1 390498277699
      Gaudenzio Meneghesso (IEEE S’95–M’97–SM’07- F’13)
      He graduated in Electronics Engineering at the University of Padova in 1992 working on the failure mechanism induced by hot-electrons in MESFETs and HEMTs. He received the Italian Telecom award for his thesis work in 1993. In 1995 he was at the University of Twente (The Netherland) with a Human Capital and Mobility fellowship (within the SUSTAIN Network) working on the dynamic behavior of protection structures against ESD. In 1997 he received the Ph.D. degree in Electrical and Telecommunication Engineering from the University of Padova working on hot-electron characterization, effects and reliability of GaAs-based and InP-based HEMT's and pseudomorphic HEMT's. Since 2011 is with University of Padova as Full Professor.
      His research interests involves mainly the Electrical characterization, modeling and reliability of several semiconductors devices: a) microwave and optoelectronics devices on III-V and III-N; b) RF-MEMS switches for reconfigurable antenna arrays; c) Electrostatic discharge (ESD) protection structures for CMOS and SMART POWER integrated circuits including ElectroMagnetic interference issues; d) organic semiconductors devices; e) photovoltaic solar cells based on various materials.
      Within these activities he published more than 600 technical papers (of which more than 80 Invited Papers and 10 best paper awards). He is reviewer of several international journals: IEEE Transactions on Electron Devices, IEEE Electron Device Letters, IEE Electronics Letters, Journal of Applied Physics, Applied Physics Letters and Semiconductor Science and Technology (IOP), Microelectronics Reliability (Elsevier).
      He served several years for the IEEE-International Electron Device Meeting (IEDM): he was in the Quantum Electronics and Compound Semiconductors sub-committee as a member in 2003, as chair in 2004 and 2005 while in 2006 and 2007 he has been in the Executive Committee as European Arrangements Chair. He is serving since 2009 in the management Committee of the IEEE International Reliability Physics (IRPS) Symposium. He is (or has been) in the steering committee of several European conferences: European Solid State Device Conference (ESSDERC), European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Heterostructures Technology Workshop (HETECH), Workshop on Compound Semiconductors Devices and Integrated Circuits held in Europe (WOCSDICE), Workshop on Compound Semiconductor Materials and Devices (WOCSEMMAD). In 2010 He entered in the IEEE EDS Adcom on different subcommittee. He has been nominated to IEEE Fellow, with the following citation: “ for contributions to the reliability physics of compound semiconductors devices”.
    • Masaaki Niwa
      Tohoku University, Japan
    • Jurriaan Schmitz
       - Silicon and Column IV , Materials, Processing and Packaging
      University of Twente
      EEMCS/MESA+
      PO Box 217
      University of Twente
      Hogekamp 3248 , Enschede 7500 AE
      The Netherlands
      Phone 1:
      +31 53 489 2726

      Fax:
      +31 53 489 1034
      Jurriaan Schmitz was born in Elst (Netherlands) in 1967. He received his M.Sc. (with honors) and Ph.D. in experimental physics from the University of Amsterdam in 1990 and 1994, respectively. His research in that period was devoted to radiation imaging detectors for Large Hadron Collider experiments. He was a CERN Summer Student in 1990.
      He joined Philips Research (Eindhoven, Netherlands) in 1994 as Senior Scientist to work on CMOS device technology, characterization and reliability. He studied transistor scaling from 0.35-µm to 90-nm technology nodes, with topics like gate depletion, boron penetration, pocket (halo) implants and shallow junctions, and developed characterization techniques for transistors with leaky dielectrics.
      In 2002 he left Philips to become Professor of Semiconductor Components at the University of Twente (Enschede, Netherlands), where he presently heads the Department of Electrical Engineering. He (co)authored over 200 scientific papers and holds 16 US patents. His research interests include CMOS post-processing, novel materials, silicon device concepts, and wafer-level electrical characterization of devices.
      Prof. Schmitz was General Chairman of the 2011 IEEE ICMTS conference, is an executive committee member of IEEE IEDM, and serves as TPC member of the ESSDERC conference. He is a member of the Editorial Advisory Board of Solid-State Electronics. He also chairs the IEEE-EDS Chapter Benelux.
    • S.C. Song
      Sr. Staff Manager
      Strategic Technology
      Qualcomm
    • John Suehle
      NIST
      USA
    • Jacobus W. Swart
       - Senior Member
      FEEC/UNICAMP - State University of Campinas
      Av. Albert Einstein 400
      Campinas, Sao Paul 13.083-970
      Brazil
      Phone 1:
      +55 19 3746 6001

      Lecture Topics: MEMS, sensors, ISFET, CNT and graphene, Advanced CMOS processes
    • Hitoshi Wakabayashi
      ​Tokyo Institute of Technology
      Japan
    • Albert Z.H. Wang
       - Fellow
      University of California
      Dept. of Electrical and Computer Engineering
      Office: 417 EBU2, Lab: 227 EBU2
      Riverside, CA 92521
      USA
      Phone 1:
      +1 951 827 2555

      Fax:
      +1 951 827 2425

      Lecture Topics:


      1. ESD-RFIC co-design techniques.
      2. Mixed-mode ESD protection circuit simulation design methodology.
      3. Above-IC ESD protection by nano technology
      4. Field-programmable ESD protection by nano technology

    • Min Yang
      IBM TJ Watson Research Center
      1101 Kitchawan Rd, Route 134
      P.O. Box 218
      Yorktown Heights, NY 10598
      USA
      Phone 1:
      +1-914-945-4922

    • Bin Zhao
       - Fellow
      ON Semiconductor
      32 Discovery, Suite 100
      Irvine, CA 92618
      USA
      Phone 1:
      +1 949 266 6800

      Fax:
      +1 614 737 6800

      Lecture Topics:


      > Analog/Mixed-Signal/RF IC and Enabling Technologies
      > High Performance VLSI Interconnect

    • Monuko du Plessis
      ​University of Pretoria
      South Africa