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EDS Webinar: ESD Protection Design for IC's: Past, Current and Future

EDS Projection Design for IC's: Past, Current and Future by Prof. Albert Wang

Abstract: Electrostatic discharge (ESD) failure is one of the most devastating IC reliability problems. Recent advances in IC technologies and designs, e.g., sub-28nm CMOS, FinFET, 3D ICs, multi-core SoC, 5G wireless ICs, power electronics and biomedical electronics, makes on-chip ESD protection design extremely challenging. For more than five decades, vast efforts have been devoted to research and development in ESD protection designs. This talk provides a comprehensive and historical review on ESD protection designs for ICs, including the past, the current and the future. The talk will cover the ESD protection basics and fundamentals, existing ESD protection solutions, current ESD protection design and ESD-IC co-design techniques, emerging full-chip ESD protection design verification CAD methods, and future ESD protection concepts.