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Fellow Evaluation Committee Chair
Samar K. Saha - Life Fellow
Samar Saha has served as the 2016-2017 President of the IEEE Electron Devices Society (EDS) and currently serving as the Senior Past President and Chairs of the J.J. Ebers Award and Fellow Evaluations Committees. He is the Chief Research Scientist at Prospicient Devices, California, USA and an Adjunct faculty in the Electrical Engineering (EE) department, Santa Clara University, USA. In the past, he has worked in various technical and management positions for National Semiconductor, LSI Logic, Texas Instruments, Philips Semiconductors, Silicon Storage Technology, Synopsys, DSM Solutions, Silterra USA, and SuVolta. In academia, he has worked as a faculty member in the EE departments at Southern Illinois University, Carbondale; Auburn University; the University of Nevada, Las Vegas; and the University of Colorado, Colorado Springs.
Dr. Saha has authored over 100 research papers; two books, entitled, FinFET Devices for VLSI Circuits and Systems (2020) and Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond (2015); one book chapter on Technology Computer-Aided Design (TCAD); and holds 12 US patents. His research interests include exploratory device and process architectures, compact modeling, renewable energy, and R & D management. He is an IEEE Life Fellow and a Fellow of the Institution of Engineering and Technology, UK.
Lecture Topics: (1) Advanced Field-Effect Transistor Device Technologies for Ultra-low Power VLSI Circuits and Systems at Nanometer Nodes; (2) Physics of Integrated Circuit Device Models for VLSI Circuit Design; (3) Thin Film Transistors for Ubiquitous Flexible Electronics; (4) Evolution of Semiconductor Devices Enabling Smart Environments and Integrated Ecosystems.
Fellow Evaluation Committee Members
Supriyo Bandyopadhyay
Department of Electrical Engineering
John D. Cressler
Fernando Guarin - Fellow
Lecture Topics: Reliability and scaling of CMOS, SiGe Reliability
Shuji Ikeda
NIRC
Shuji Ikeda (M’91-SM’02-F’04) received the B.S. degree in Physics, PhD. in Electrical Engineering from Tokyo Institute of Technology, Tokyo, Japan in 1978 and 2003 respectively and the M.S. degree in Electrical Engineering from Princeton University, Princeton, New Jersey, USA in 1987. He joined Semiconductor and Integrated Circuit Group, Hitachi ltd., Tokyo, Japan in 1978, where he was engaged in research and development of state of the art SRAM process and devices. He was also working on developing process technology for LOGIC, embedded memories, and CMOS power RF devices and on transferring technology to mass production line. He invented some of the outstanding structures for SRAM. He pioneered process to implement new materials in mass production, including W-polycide, Al-Cu-Si in 1984 and in-situ phosphorus-doped-polysilicon in 1990. He is the first to realize Lightly Doped Drain (LDD) in production to suppress Hot Carrier Injection in 1984. He also firstly implemented polyimide coat of the chip to immune SER caused by alpha particle from the resin covers the chip. In October 2000, he joined Trecenti Technologies Inc. He developed new process scheme with aggressive reduction of process time and suitable for single-wafer processing. That achieved less than 0.25days/layer cycle time. In April 2005, he joined ATDF at Austin Texas, as a Director of Technology. Where he develops various kinds of technologies includes scaled CMOS, non-classical CMOS, new materials and tools. He established tei Technology LLC in May 2008, Omni Water Solutions LLC, in 2009 at Austin Texas. He started tei Solutions Inc in Tsukuba, Ibaraki, Japan in 2010, where, he manages R&D foundry developing new devices, process technologies for VLSIs. He also integrates emerging technology onto semiconductor manufacturing technology to create innovative products/businesses. Due to his contributions to 200 MHz RISC microprocessor, he got 1999 R&D 100 Award. He served as subcommittee and executive committee member of IEDM from 1993 to 2002. He introduced Manufacturing Session in 1998 and chaired IEDM in 2002. He was a member of EDS Administrative Committee from 2005 to 2010. He was a technical program member for VLSI Technology Symposium in 2007 and 2008. He serves as a chairman of VLSI committee of EDS from 2009 and AdHoc Committee on Asia EDS Conference from 2014.
Veena Misra
Dept. of Electrical Engineering
Tomas Palacios - Compound Semiconductor Devices; Emerging Technologies and Devices; Solid-State Power and High Voltage Devices
Tomás Palacios is a Professor in the Department of Electrical Engineering and Computer Science at MIT. He received his PhD from the University of California - Santa Barbara in 2006, and his undergraduate degree in Telecommunication Engineering from the Universidad Politécnica de Madrid (Spain). His current research focuses on demonstrating new electronic devices and applications for novel semiconductor materials such as graphene and gallium nitride. His work has been recognized with multiple awards including the Presidential Early Career Award for Scientists and Engineers, the IEEE George Smith Award, and the NSF, ONR, and DARPA Young Faculty Awards, among many others. Prof. Palacios has authored more than 300 contributions in international journals and conferences, 10 of which have received a best-paper award, as well as 5 book chapters and more than 30 patents. Prof. Palacios is the founder and director of the MIT MTL Center for Graphene Devices and 2D Systems, as well as the Chief Advisor and co-founder of Cambridge Electronics, Inc.
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