Compact Modeling Committee
Compact Modeling Committee Chair
Yogesh Singh Chauhan - Device and Process Modeling
· Modeling and Simulation of Negative Capacitance Transistors
· Compact Modeling of GaN HEMTs using industry standard ASM-HEMT model
· Physics and Modeling of FinFET and Nanosheet Transistors
· Analog and RF Modeling in BSIM-BULK model
· Physics and Modeling of FDSOI Transistors
Yogesh Singh Chauhan is an associate professor at Indian Institute of Technology Kanpur (IITK), India. He was with Semiconductor Research & Development Center at IBM Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; University of California Berkeley during 2010-2012; and ST Microelectronics during 2003-2004. He is the developer of several industry standard models: ASM-GaN-HEMT model, BSIM-BULK model (formerly BSIM6), BSIM-CMG model and BSIM-IMG model. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs. His research interests are characterization, modeling, and simulation of semiconductor devices.
He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the member of IEEE-EDS Compact Modeling Committee and fellow of Indian National Young Academy of Science (INYAS). He is the founding chairperson of IEEE Electron Devices Society U.P. chapter and Vice-chairperson of IEEE U.P. section. He has published more than 200 papers in international journals and conferences.
He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award, Humboldt fellowship and Swarnajayanti fellowship in 2018. He has served in the technical program committees of IEEE International Electron Devices Meeting (IEDM), IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), IEEE European Solid-State Device Research Conference (ESSDERC), IEEE Electron Devices Technology and Manufacturing (EDTM), and IEEE International Conference on VLSI Design and International Conference on Embedded Systems.
Compact Modeling Committee Members
Hamdy Abd Elhamid
Wladek Grabinski - Senior Member
Chang-Hyun Kim is an Assistant Professor of Electronic Engineering at Gachon University, Korea. He earned his B.Sc. in information display from Kyung Hee University, Korea and received his Ph.D. in physics from the Ecole Polytechnique, France. Prior to joining the faculty, he held fellowship positions at Columbia University, USA, the French National Center for Scientific Research (CNRS), and Gwangju Institute of Science and Technology, Korea. Dr. Kim's research is focused on combining experimental and modeling approaches to improving the performance of organic and hybrid nanoelectronics. He published over 40 peer-reviewed papers and his scientific contribution has been recognized by several awards, including the Korean Ministry of Education Research Fellowship, and the IEEE International Symposium on Next-Generation Electronics Best Paper Award.
Marek Mierzwinski - Software Engineer
Marek Mierzwinski is an R&D engineer at Keysight Technologies, responsible for compact models for their commercial circuit simulator. He started at Hewlett Packard in 1979 as a product engineer in the III-V fab, working on microwave devices including BJTs, FETs, surface acoustic wave resonators, and micromachined high frequency thermocouple power sensors. As an R&D project manager he was responsible for their first modulation doped FET Integrated Circuit process. He later worked in device characterization and then as R&D project manager for the analog circuit simulator behind the HP Advanced Design System (ADS). In 2002 he co-founded Tiburon Design Automation, which developed the industry’s first commercial Verilog-A compiler, allowing compact transistor models to be easily implemented in multiple simulators. He left Tiburon-DA in 2012 and returned to Keysight. Marek graduated with a B.S. in Engineering Physics from Cornell University and received his Masters and Ph.D. from Stanford University in Electrical Engineering.
Marcelo Pavanello - Senior Member
Marcelo Antonio Pavanello (S´99-M´02-SM´05) received the Electrical Engineering degree from FEI University in 1993, receiving the award “Instituto de Engenharia” given for the best student among all the modalities of engineering programs offered at FEI. He received the M. Sc. and Ph. D. degrees in 1996 and 2000, respectively, in Electrical Engineering (Microelectronics) from University of São Paulo, Brazil. From August to December 1998 he was with Laboratoire de Microélectronique from Université Catholique de Louvain (UCL), Belgium, working in the fabrication and electrical characterization of novel channel-engineered Silicon-On-Insulator (SOI) transistors. From 2000 to 2002 he was with the Center of Semiconductor Components and Nanotechnologies, State University of Campinas, Brazil, where he worked as a post-doctoral researcher in the development of a CMOS n-well process. Since 2003 he joined FEI University where he is now Full Professor at Electrical Engineering Department. In 2008 he has been with UCL as a visiting professor. Dr. Pavanello is Senior member of The IEEE and Brazilian Microelectronics Society. He is also Research Associate to the National Council for Scientific Development (CNPq), Brazil. Since 2007 he serves as IEEE Electron Devices Society (EDS) Distinguished Lecturer and has been nominated to the Compact Modeling Technical Committee of EDS in 2018. He is author and co-author of more than 300 technical papers in peer-reviewed journals and conferences, and author/editor of 6 books. Dr. Pavanello coordinates several research projects fomented by Brazilian agencies like FAPESP, CNPq and Capes. He also supervised several Ph. D. dissertations, M. Sc. thesis and undergraduate projects in Electrical Engineering. His current interests are the compact modeling, fabrication, electrical characterization and simulation of SOI CMOS transistors with multiple gate configurations and silicon nanowires; the wide temperature range of operation of semiconductor devices; the digital and analog operation of novel channel-engineered SOI devices and circuits.
-Junctionless Nanowire Transistors: Electrical Characteristics and Compact Modeling;
-Physics and Electrical Characterization of Multiple-Gate Transistors (Nanowires and FInFETs) in a Wide Temperature Range of Operation;
-Impact of Channel Engineering on SOI Devices and Circuits;
-Operation and Modeling of Silicon-On-Insulator MOSFETs in Cryogenic Environments.
Mike Schwarz - EDS Newsletter Regional Editor
Mike Schwarz (M'15-SM'18) received his Ph.D. with honors from the Universitate Rovira i Virgili on the subject of compact modeling of Schottky barrier multiple-gate FETs. He was the recipient of the Friedrich Dessauer Prize for the best diploma thesis about multiclass support vector machines in 2008, and the URV Graduated Student Meeting on Electronic Engineering Award for the best oral presentation for a paper about an analytical model for the electric field in Schottky barrier double-gate MOSFETs in 2010.
From 2013-2020 he was with the Robert Bosch GmbH, working with the RnD department on design, layout, modeling and process and device simulation of MEMS sensors and systems. From 2016-2020 he was lead of the diode design and process-/device simulation in the MEMS RnD department. In 2018 he became IEEE Senior Member. Since 2020 he is with the TH Mittelhessen - University of Applied Sciences as Professor for "Embedded Systems and Simulation.". His current research interests are Schottky barrier MOSFET devices, neuropmorphic devices, compact modeling and cryogenic applications.
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