Compact Modeling Committee
Compact Modeling Committee Chair
Benjamin Iniguez - Senior Member
Benjamin Iñiguez obtained the Ph D in Physics in 1992 and 1996, respectively, from the Universitat de les Illes Balears (UIB). From February 1997 to September 1998 he was working as a Postdoctoral Researcher at the Rensselaer Polytecnhnic Institute in Troy (NY, USA). From September 1998 to January 2001 he was working as a Postdoctoral Scientist in the Université catholique de Louvain (Louvain-la-Neuve, Belgium), supported by two Marie Curie Fellowships from the European Commission. In February 2001 he joined the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA)of the Universitat Rovira i Virgili (URV), in Tarragona, Catalonia, Spain) as Titular Professor. In February 2010 he became Full Professor at URV. He obtained the Distinction from the Generalitat for the Promotion of University Research in 2004 and the ICREA Academia Award (the highest award for university professors in Catalonia, from ICREA Institute) in 2009 and 2014, for a period of 5 years each. He led one EU-funded project (“COMON”, 2008-12) devoted to the compact modeling of nanoscale semiconductor devices and he is currently leading one new EU-funded project (DOMINO, 2014-18) targeting the compact modeling of organic and oxide TFTs. His main research interests are the characterization, parameter extraction and compact modelling of emerging semiconductor devices, in particularorganic and oxide Thin-Film Transistors, nanoscale Multi-Gate MOSFETs and GaN HEMTs. He has published more than 150 research papers in international journals and more than 130 abstracts in proceedings of conferences.
Compact device modeling
Semiconductor device parameter extraction
Physics of Thin-Film Transistors
Graphene and TMD devices
Compact Modeling Committee Members
Hamdy Abd Elhamid
Yogesh Singh Chauhan - Device and Process Modeling
· Modeling and Simulation of Negative Capacitance Transistors
· Compact Modeling of GaN HEMTs using industry standard ASM-HEMT model
· Physics and Modeling of FinFET and Nanosheet Transistors
· Analog and RF Modeling in BSIM-BULK model
· Physics and Modeling of FDSOI Transistors
Yogesh Singh Chauhan is an associate professor at Indian Institute of Technology Kanpur (IITK), India. He was with Semiconductor Research & Development Center at IBM Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; University of California Berkeley during 2010-2012; and ST Microelectronics during 2003-2004. He is the developer of several industry standard models: ASM-GaN-HEMT model, BSIM-BULK model (formerly BSIM6), BSIM-CMG model and BSIM-IMG model. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs. His research interests are characterization, modeling, and simulation of semiconductor devices.
He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the member of IEEE-EDS Compact Modeling Committee and fellow of Indian National Young Academy of Science (INYAS). He is the founding chairperson of IEEE Electron Devices Society U.P. chapter and Vice-chairperson of IEEE U.P. section. He has published more than 200 papers in international journals and conferences.
He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award, Humboldt fellowship and Swarnajayanti fellowship in 2018. He has served in the technical program committees of IEEE International Electron Devices Meeting (IEDM), IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), IEEE European Solid-State Device Research Conference (ESSDERC), IEEE Electron Devices Technology and Manufacturing (EDTM), and IEEE International Conference on VLSI Design and International Conference on Embedded Systems.
Wladek Grabinski - Senior Member
Chang-Hyun Kim is an Assistant Professor of Electronic Engineering at Gachon University, Korea. He earned his B.Sc. in information display from Kyung Hee University, Korea and received his Ph.D. in physics from the Ecole Polytechnique, France. Prior to joining the faculty, he held fellowship positions at Columbia University, USA, the French National Center for Scientific Research (CNRS), and Gwangju Institute of Science and Technology, Korea. Dr. Kim's research is focused on combining experimental and modeling approaches to improving the performance of organic and hybrid nanoelectronics. He published over 40 peer-reviewed papers and his scientific contribution has been recognized by several awards, including the Korean Ministry of Education Research Fellowship, and the IEEE International Symposium on Next-Generation Electronics Best Paper Award.
Marcelo Pavanello - Senior Member
Marcelo Antonio Pavanello (S´99-M´02-SM´05) received the Electrical Engineering degree from FEI University in 1993, receiving the award “Instituto de Engenharia” given for the best student among all the modalities of engineering programs offered at FEI. He received the M. Sc. and Ph. D. degrees in 1996 and 2000, respectively, in Electrical Engineering (Microelectronics) from University of São Paulo, Brazil. From August to December 1998 he was with Laboratoire de Microélectronique from Université Catholique de Louvain (UCL), Belgium, working in the fabrication and electrical characterization of novel channel-engineered Silicon-On-Insulator (SOI) transistors. From 2000 to 2002 he was with the Center of Semiconductor Components and Nanotechnologies, State University of Campinas, Brazil, where he worked as a post-doctoral researcher in the development of a CMOS n-well process. Since 2003 he joined FEI University where he is now Full Professor at Electrical Engineering Department. In 2008 he has been with UCL as a visiting professor. Dr. Pavanello is Senior member of The IEEE and Brazilian Microelectronics Society. He is also Research Associate to the National Council for Scientific Development (CNPq), Brazil. Since 2007 he serves as IEEE Electron Devices Society (EDS) Distinguished Lecturer and has been nominated to the Compact Modeling Technical Committee of EDS in 2018. He is author and co-author of more than 300 technical papers in peer-reviewed journals and conferences, and author/editor of 6 books. Dr. Pavanello coordinates several research projects fomented by Brazilian agencies like FAPESP, CNPq and Capes. He also supervised several Ph. D. dissertations, M. Sc. thesis and undergraduate projects in Electrical Engineering. His current interests are the compact modeling, fabrication, electrical characterization and simulation of SOI CMOS transistors with multiple gate configurations and silicon nanowires; the wide temperature range of operation of semiconductor devices; the digital and analog operation of novel channel-engineered SOI devices and circuits.
-Junctionless Nanowire Transistors: Electrical Characteristics and Compact Modeling;
-Physics and Electrical Characterization of Multiple-Gate Transistors (Nanowires and FInFETs) in a Wide Temperature Range of Operation;
-Impact of Channel Engineering on SOI Devices and Circuits;
-Operation and Modeling of Silicon-On-Insulator MOSFETs in Cryogenic Environments.
Mike Schwarz - EDS Newsletter Regional Editor
Automotive Electronics, Engineering Sensor Technology Center 4 - Design, Simulation and Layout Sensors
Mike Schwarz received the Diploma degree from the University of Applied Sciences Giessen-Friedberg, Giessen, Germany, in 2008 and the M.S. degree in electrical engineering from the Universitat Rovira i Virgili, Tarragona, Spain, in 2009. During 2008-2013, he was Research Assistant - Ph.D. student at Device Modeling Research Group, NanoP, Technische Hochschule Mittelhessen, Giessen, Germany. He received his Ph.D. degree with honors from the Universitat Rovira i Virgili in October 2012 on the subject of compact modeling of Schottky barrier multiple-gate FETs. Mike was the recipient of the Friedrich Dessauer Prize for the best diploma thesis about multiclass support vector machines in 2008 and the URV Graduated Student Meeting on Electronic Engineering Award for the best oral presentation for a paper about an analytical model for the electric field in Schottky barrier double-gate MOSFETs in 2010. Since 2013 he is with the Robert Bosch GmbH, working in the R&D department on design, layout, modeling and process and device simulation of MEMS sensors and systems. Since 2016 he is leader of the diode design in the MEMS R&D department. His current research interests are simulation and compact modeling of Schottky Barrier MOSFET devices and simulation and compact modeling of neuromorphic applications. He is member of the scientific committee of MIXDES conference. He is member of the NanoP, Giessen, Germany.
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