VLSI Technology & Circuits Committee
Objective
The objective of the VLSI Technology and Circuits Committee is to identify new/hot areas of interest to the Electron Devices and Solid-State Circuits communities. Based on the nature of the areas, we will recommend any or all of the following:
Initiate topical workshops of current interest (attached to existing conferences or start new ones)
Special Issues for major publications (e.g., J-Eds, T-ED)
Panel session topics for EDS sponsored/co-sponsored conferences
Special Sessions for EDS sponsored/co-sponsored conferences
This committee strongly suppors EDTM (Electron Devices Technology and Manufacturing) conference which was estableshed by our activity.
Membership
This is a non-voting Ex-Officio Forum member position with a two-year term and serves up to two-terms. We limit the membership terms so that new ideas can be generated, incorportated, and executed.
Operation
Operation of this committee is done mainly by email. We have face-to-face meetings in conjunction with the EDS BoG Meeting. There are two BoG meetings a year, with one being held in conjunction with IEDM and the other is held in May or June in conjunction with another EDS sponsored conference or event. The other opportunity to have face-to-face (ad-hoc) meetings is in conjunction with EDS sponsored conference such as EDTM (in Asia around March) and ESSDERC (in Europe around September). This means each quarter, members have the chance to meet in person. Since member's are located globally this helps communication among all committee members.
History
The VLSI Technology and Circuits Technical Committee was formed in 1998 under the leadership of Prof. Charles G. Sodini (MIT), followed by Dr. H.-S. Philip Wong (IBM), Werner Weber (Infineon), Dr. James A. Hutchby (SRC) and Dr. Bin Zhao (Freescale Semiconductor). Since its formation, the VLSI Committee has chartered its missions to identify new technical trends, to help foster new technical concepts, and to serve the emerging needs of the Electron Devices and Solid-State Circuits communities in VLSI. The committee members include many well recognized technical experts representing a very wide spectrum of technical expertise in VLSI devices, technology, and circuits. Every year, the committee brainstorms (by email) on ideas that are suitable for a new workshop, special issue for a journal, panel sessions, and special sessions for conferences. Committee members then take these ideas forward and find a way to make them happen, either by being the organizers themselves, or by finding suitable organizers for the topic. We work closely together with journal editors and conference organizers. Especially in the case of new workshops, it is much easier to attach the new workshop to existing conferences rather than to start new. EDTM conference was established and started in 2017 based on our activity and many committee members are supporting this conference.
Contact
If you have ideas for a new workshop, a special issue for journals, or topics for panel sessions and special sessions for conferences, please contact current committee members. If you would like to volunteer in the committee or have suggestions and comments to the activities of this committee, please contact Kazunari Ishimaru.
Chair
Kazunari Ishimaru
Toshiba Memory Corporation
kazu.ishimaru@toshiba.co.jp
Any comments, ideas, and suggestions related to the field of VLSI Technology and Circuits are sincerely welcome!
Please click here to view the committee's article from the April 2017 edition of the EDS Newsletter.
VLSI Technology and Circuits Committee Chair
VLSI Technology and Circuits Committee Members
Shuji Ikeda (M’91-SM’02-F’04) received the B.S. degree in Physics, PhD. in Electrical Engineering from Tokyo Institute of Technology, Tokyo, Japan in 1978 and 2003 respectively and the M.S. degree in Electrical Engineering from Princeton University, Princeton, New Jersey, USA in 1987. He joined Semiconductor and Integrated Circuit Group, Hitachi ltd., Tokyo, Japan in 1978, where he was engaged in research and development of state of the art SRAM process and devices. He was also working on developing process technology for LOGIC, embedded memories, and CMOS power RF devices and on transferring technology to mass production line. He invented some of the outstanding structures for SRAM. He pioneered process to implement new materials in mass production, including W-polycide, Al-Cu-Si in 1984 and in-situ phosphorus-doped-polysilicon in 1990. He is the first to realize Lightly Doped Drain (LDD) in production to suppress Hot Carrier Injection in 1984. He also firstly implemented polyimide coat of the chip to immune SER caused by alpha particle from the resin covers the chip. In October 2000, he joined Trecenti Technologies Inc. He developed new process scheme with aggressive reduction of process time and suitable for single-wafer processing. That achieved less than 0.25days/layer cycle time. In April 2005, he joined ATDF at Austin Texas, as a Director of Technology. Where he develops various kinds of technologies includes scaled CMOS, non-classical CMOS, new materials and tools. He established tei Technology LLC in May 2008, Omni Water Solutions LLC, in 2009 at Austin Texas. He started tei Solutions Inc in Tsukuba, Ibaraki, Japan in 2010, where, he manages R&D foundry developing new devices, process technologies for VLSIs. He also integrates emerging technology onto semiconductor manufacturing technology to create innovative products/businesses. Due to his contributions to 200 MHz RISC microprocessor, he got 1999 R&D 100 Award. He served as subcommittee and executive committee member of IEDM from 1993 to 2002. He introduced Manufacturing Session in 1998 and chaired IEDM in 2002. He was a member of EDS Administrative Committee from 2005 to 2010. He was a technical program member for VLSI Technology Symposium in 2007 and 2008. He serves as a chairman of VLSI committee of EDS from 2009 and AdHoc Committee on Asia EDS Conference from 2014.
Lecture Topics
- Designer Ge quantum-dot phototransistors for highly-integrated, broadband optical interconnects
- Germanium quantum dots for functional charge sensing/metrology devices
- The Unique Optoelectronic and Energy-Conversion Devices based on Ge/Si/O Interactions
- Self-organized Ge QD/SiO2/SiGe-recess channel FETs
D NIRMAL received the B.E. degree in Electrical and Electronics from Anna University, Chennai, India in 2005, and the M.E. degree in VLSI Design from Karunya University and Ph.D. degree in Information and communication from Anna University, Chennai, India in 2012. He is currently an Associate professor of Electronics and communication engineering at Karunya Institute of technology and sciences, Coimbatore, India.
His research interest includes Nano devices, GaN HEMT, VLSI Design, Optoelectronics and Device fabrication. He has published several papers in Journal and conferences.
Among his honours, he is a recipient of Shir.P.K.Das Memorial Best Faculty Award in the Year 2013 and Intuition of Engineers Young Engineering Award in 2017. Best researcher award from karunya University in the year 2014.
He is Editor of Microelectronics Journal and International journal of Electronics and communication Engineering of Elsevier publisher form 2014 and 2016 respectively.
He is also currently working in funded project from Defense Research and Development organization, Government of India and Tamil Nadu state Council for science and technology, India.
He is currently a Chair of IEEE ED Coimbatore Chapter . He is a Senior member of IEEE, Member of IETE, SSI , ISTE and VSI Societies.
Aaron Voon-Yew Thean is a Professor of Electrical and Computer Engineering at the National University of Singapore (NUS). He is also a consulting Fellow to IMEC, a Nano-electronic Research Center, based in Belgium. Prior to joining NUS in 2016, Aaron served as IMEC’s Vice President of Logic Technologies and the Director of the Logic Devices Research. At IMEC, he directed the research and development of advanced device technologies ranging from ultra-scaled FinFETs, Nanowire FETs, to III-V/Ge Channels, Tunnel FETs to emerging Beyond CMOS logic nano-device architectures based on Spintronics and 2-D materials. He has been involved in Design and Process Technology Co-optimizations (DTCO) of emerging technologies targeting 7nm, 5nm, and beyond. Before 2011, he was with Qualcomm’s CDMA technologies in San Diego, California, USA. There, he led the Strategic Silicon Technologies Group responsible for new System-On-Chip technology definition for upcoming Qualcomm technologies. From 2007 to 2009, Aaron served as the International Semiconductor Development Alliance (ISDA) FEOL and Device Manager at IBM, where he co-led an eight-company alliance device/process team to develop the 28-nm and 32-nm low-power bulk CMOS technology at IBM East Fishkill, New York. His team developed the Industry’s first foundry-compatible Gate-First High-k Metal-Gate (HKMG) with novel SiGe channel Low-Power bulk CMOS technologies. It enabled some of today’s most successful smart mobile devices in production by the foundry partners. Before IBM, Aaron was a senior staff scientist with Freescale Semiconductor and Motorola’s Advanced Product Research and Development Laboratory (APRDL). He subsequently led the Novel Device Research Group there in Austin, Texas. He performed path-finding research on a variety of advanced semiconductor devices that included Strained-Si-On-Silicon, FinFETs, FDSOI, and Nano-crystal Flash Memory. Aaron graduated from the University of Illinois at Champaign-Urbana, USA, where he received his B.Sc. (Highest Honors & Graduated as Edmund J. James’ Scholar), M.Sc., and Ph.D. degrees in Electrical Engineering. He was awarded the 2001 Gregory Stillman Semiconductor Research Award for his Ph.D. work. He has published over 300 technical papers and holds more than 50 U.S. patents for inventions in the field of advanced electronics. Among his notable recognitions include the 2014 Compound Semiconductor Industry Innovation award for his research group’s break-though III-V FinFET work. In 2013, he was given the Best Collaboration Award from Samsung Electronics Korea for R&D collaborations contributing towards its Semiconductor R&D Center. Aaron received the 2010 Young Alumni Achievement Award from his Alma Mater, University of Illinois, for his contribution to advanced transistor R&D, as well.
Shimeng Yu received the B.S. degree in microelectronics from Peking University, Beijing, China in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, USA in 2011, and in 2013, respectively. He is currently an assistant professor of electrical engineering and computer engineering at Arizona State University, Tempe, AZ, USA.
His research interests are emerging nano-devices and circuits with a focus on the resistive memories for different applications including machine/deep learning, neuromorphic computing, monolithic 3D integration, hardware security, radiation-hard electronics, etc. He has published >60 journal papers and >100 conference papers with citations >5500 and H-index 34.
Among his honors, he is a recipient of the Stanford Graduate Fellowship from 2009 to 2012, the IEEE Electron Devices Society Masters Student Fellowship in 2010, the IEEE Electron Devices Society PhD Student Fellowship in 2012, the DOD-DTRA Young Investigator Award in 2015, the NSF Faculty Early CAREER Award in 2016, and the ASU Fulton Outstanding Assistant Professor in 2017, and the IEEE Electron Devices Society Early Career Award in 2017.
He did summer internship in IMEC, Belgium in 2011, and IBM TJ Watson Research Center in 2012. He held visiting faculty position in Air Force Research Laboratory in 2016. He served the Technical Program Committee for IEEE International Symposium on Circuits and Systems (ISCAS) 2015-2017, ACM/IEEE Design Automation Conference (DAC) 2017-2018, and IEEE International Electron Devices Meeting (IEDM) 2017-2018, etc.
