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Editor-in-Chief and Editors
We are currently in the process of selecting a world-class editorial board to edit and approve manuscripts for inclusion in the J-EDS.
If you are interested in serving as a J-EDS editor, please contact the current Editor-In-Chief Enrico Sangiorgi for more information.
If you wish to be added to the list of potential reviewers in the EDS database, please contact the EDS headquarters. Kindly provide your full name, email address, and area of expertise.
Click on the names below to read each editor's biography.
Enrico Sangiorgi - Fellow Enrico Sangiorgi (F’05) received the Laurea degree in electrical engineering from the University of Bologna, Italy, in 1979. In 1983, 1984, and 1991, he was a Visiting Scientist at the Center for Integrated Systems, Stanford University, Stanford, California, for approximately three years. From 1985 to 2001, he was a consultant at Bell Laboratories, Murray Hill, NJ, where he was a Resident Visitor for more than three years. In 1993, he was appointed Full Professor of Electronics at the University of Udine, Italy, where he started the Electrical Engineering Program and the microelectronic group. In 2002, he joined the University of Bologna, where he is currently in charge of the nanomicro- electronics group at the Campus of Cesena. From 2005 to 2011 he has been the Director of Consorzio Nazionale Interuniversitario per la Nanoeletronica (IU.NET – Italian Universities Nanoelectronic Team), a Legal Consortium grouping nine University Groups active in the field of Nanoelectronics. In 2005 he has been appointed member of the CATRENE Scientific Committee. Since 2006 he is the Vice Chairman of the Scientific Community Council (SCC) of ENIAC (the European Nanoelectronics Initiative Advisory Council). In 2007 he has been appointed member of the Steering Board of AENEAS, the private section of the ENIAC European Technology Platform. In 2008 he has been appointed CEO of Rinnova srl., a new company founded by the University of Bologna aiming to bring research and innovation to SME’s. From 2008 to 2012 he has been the Dean of the Second School of Engineering at the University of Bologna. In 2012 he has been appointed Director of the Department of Electrical and Electronic Engineering – Guglielmo Marconi – of the University of Bologna. Since 2014 he is the Director of the SINANO Institute, International Organization grouping 23 European Institutions active in the field of nanoelectronics. From 1994 to 2009 he has been Editor of IEEE Electron Device Letters. He has been the Guest Editor of several Special Issues on major scientific journals such as IEEE Transactions on Electron Devices, Solid State Electronics, etc. He has been a member of the Technical Committees of several International Conferences on Electron Devices: IEDM (’91-96; ’04-’06), ESSDERC (‘99-present), INFOS (’95-03), ULIS (’00-‘08), etc. Since 2011 he is a member of the Steering Board of the IEEE Journal of Photovoltaics. Enrico Sangiorgi is a Fellow of the IEEE, Distinguished Lecturer of the Electron Device Society, he has been Chairman of the Electron Device Society TCAD Technical Committee from 2004 to 2011 member of the Cledo Brunetti Award Committee and Education Award Committee of the EDS. Since 2011 he is elected member of the EDS AdCom. Since 2013 he is a member of the EDS Fellows Evaluation Committee. He has been involved in several European Projects of the 5, 6, and 7 FP with Management Responsibilities, and he has acted as Project Reviewer for the European Commission. The research interests of Enrico Sangiorgi, developed in cooperation with research centers and companies such as Bell Labs., Philips, Infineon Tech., ST Microelectronics, IMEC, and CEA-LETI, include the physics, characterization, modeling, and fabrication of silicon solid-state devices and integrated circuits. In particular he has been working on several aspects of device scaling, its technological, physical, and functional limits, as well as device reliability for silicon CMOS and bipolar transistors. In order to tackle and eventually overcome the hurdles of device scaling, down to the ultimate physical and technological limits, he has devised and developed several original concepts and methods in the characterization and modeling of nanoscale silicon devices. Recently his interests included the physics and modeling of Photo-voltaics devices where he has worked on several aspects of device optimization. Enrico Sangiorgi coauthored 34 papers presented at the International Electron Devices Meeting (IEDM) Conference, and overall more than 250 papers on major journals and conference proceedings. Lecture Topics: Nanodevices modeling and simulation Photovoltaics devices and technologies Energy Harvesting devices, technologies and systems Constantin Bulucea - Distinguished Member of the Technical Staff Constantin Bulucea (S'69–M'70–SM'88–F'04- LF'13) was born in Râmnicu Valcea, Romania. In 1969, he got a one-year government scholarship at the University of California, Berkeley, where he received a M.S. degree in Electrical Engineering. In 1974, he received his Doctor degree in Electronis from the Polytechnic Institute of Bucharest with a thesis on hot-carrier injection in silicon. His original results were communicated at IEDM and published in the old (W. Crawford Dunlap’s) Solid-State Electronics. In Romania, he created the Annual Conference on Semiconductors, now an international IEEE event. His best known contribution from that period is the explanation of Grove’s breakdown voltage collapse in silicon gate-controlled devices as a breakdown-location switching phenomenon, as proven by 2-D computer calculations and measurements. Among his “firsts” from the same time is the direct proof, by DC recordings (rather than by capacitive inferences) of nA-range hot-carrier currents through silicon dioxide. In 1886, Dr. Bulucea defected to the US, where he first developed a device/process architecture for rugged trench power DMOS transistors, while working for Siliconix (1987-1989). His inventive design became a world standard in the following years. Later on, at National Semiconductor (NS), he was a member of the Fairchild Research Center, then joined the company’s process development group. There, he enjoyed the last years of Silicon Valley's "Happy Scaling" as the architect of several CMOS processes for high-performance analog and mixed-signal applications (2000-2010). In 2011, he became a Distinguished Member of the Technical Staff of Texas Instruments (TI), as a result of TI's acquisition of NSC. Throughout his tenure at NS and TI, he received three Patent of the Year awards, in recognition of the use of his inventions in high-volume manufacturing. He has published over 50 technical articles in major journals and has 70 issued US patents. In 2001, he was elected an Honorary Member of the Romanian Academy and in 2004 became an IEEE Fellow "for contributions to transistor engineering in the area of power electronics". Dr. Bulucea has been a member of the Technical Committees of the Bipolar Circuits and Technology Meeting (BCTM) and of the VLSI Technology Symposium. Between 2004 and 2012 he was the editor of IEEE Electron Device Letters (EDL) for analog and mixed-signals technology. His IEEE responsibilities include membership in the IEEE/EDS Fellow Evaluation Committee (2018, 2019) and the IEEE/EDS Publications Committee (current). Subhananda Chakrabarti Subhananda Chakrabartir received his M.Sc. and Ph.D. degrees from the Department of Electronic Science, University of Calcutta, Kolkata, India in 1991 and 2000, respectively. He was a Lecturer in the Dept. of Physics, St. Xavier’s College, Kolkata. He has been a Senior Research Fellow with the University of Michigan, Ann Arbor, from2001 to 2005, a Senior Researcher with Dublin City University, Dublin City, Ireland, from 2005 to 2006, and a Senior Researcher (RA2) with the University of Glasgow, Glasgow, U.K., from 2006 to 2007. He joined as an Assistant Professor in the Department of Electrical Engineering, IIT Bombay, Mumbai, India, in 2007.Presently, he is a Professor in the same department. He has extensively researched in molecular beam epitaxial(MBE) growth, characterization, and fabrication of compound (III-V) GaAs-based semiconductor optoelectronic materials and devices, such as intersubband infrared photodetectors etc. He has been the first to demonstrate complete indigenous development Infrared Photodetector based Focal Plane Array in India. In II-VI (ZnO) based research, he has demonstrated stable p-doping through Plasma Immersion Ion Implantation (PIII) technique and subsequently demonstrated a homojunction ZnO-based UV-LED. He is a fellow of the Institution of Electrical and Telecommunication Engineers (IETE) India, Member of the IEEE, MRS USA, SPIE USA etc. He is the medal recipient of the Materials Research Society of India. Recently, he was awarded NASI-Reliance Industries Platinum Jubilee Award for Application Oriented Innovations in Physical Sciences for the year 2016. He has authored more than 200 papers in international journals and conferences. He has also co-authored a couple of book chapters on intersubband quantum dot detectors. His four (4) research monographs with Springer are in press. Dr. S. Chakrabarti has served as reviewer for a number of international journals of repute such as Applied Physics Letters, Nature Scientific Report, IEEE Photonics Technology Letters, IEEE Journal of Quantum Electronics, Journal of Alloys and Compound, Material Research Bulletin etc. Mansun J. Chan - Fellow Lecture Topics: - Nano-device physics and technology Biography: Mansun Chan (S’92-M’95-SM’01-F’13) received Ph.D. degrees from the UC, Berkeley in 1995. He is one of the major contributors to the unified BSIM model for SPICE, which has been accepted by most US companies and the Compact Model Council (CMC) as the first industrial standard MOSFET model. In January 1996, he has joined the EEE faculty at Hong Kong University of Science and Technology. After that, he developed a SOI MOSFET model, which has been adopted by UC Berkeley as the core of the BSIMSOI model. Between July 2001 and December 2002, he was a Visiting Professor at University of California at Berkeley and the Co-director of the BSIM program. In this capacity, he has successfully completed the technology transfer of BSIM3SOI to be the first industrial standard SOI MOSFET model. In addition to device modeling, Prof. Chan’s current research interests also include nano-transistor fabrication technology, carbon-based device physics, printable transistors, 3D integrated circuits, bio-sensors and cloud computing based simulation platform. He is current working on an interactive modeling and online simulation (i-MOS) platform to facilitate the interactions between model developers and circuit designers using the Internet technology. Prof. Chan is a recipient of the UC Regents Fellowship, Golden Keys Scholarship for Academic Excellence, SRC Inventor Recognition Award, Rockwell Research Fellowship, R&D 100 award (for the BSIM3v3 project), Teaching Excellence Appreciation award, Distinguished Teaching Award and the Shenzhen City Technology Innovation Award by the Chinese Government. He is a Fellow and Distinguished Lecturer of IEEE. Nadine Collaert Nadine Collaert received the M.S. and Ph.D. degrees in electrical engineering from the ESAT Department, KU Leuven, Belgium, in 1995 and 2000, respectively. Since then, she has been involved in the theory, design, and technology of FinFET devices, emerging memory devices, transducers for biomedical applications and the integration and characterization of biocompatible materials e.g. carbon-based materials. From 2012 until April 2016 she was program manager of the imec LOGIC program, focusing on high mobility channels, TFET and nanowires. Since April 2016 she is a distinguished member of technical staff, responsible for the research on novel CMOS scaling approaches based on heterogeneous integration of new materials with Si and new material-enabled device and system approaches to increase functionality. She has authored or co-authored more than 300 papers in international journals and conference proceedings, and she holds more than 10 patents in the field of device design and process technology. She has been a member of the CDT committee of the IEDM conference and she is still a member of the Program Committees of the international conferences ESSDERC, ULIS/EUROSOI, NMDC, S3S and the VLSI Technology Symposium. Shuji Ikeda Shuji Ikeda (M’91-SM’02-F’04) received the B.S. degree in Physics, PhD. in Electrical Engineering from Tokyo Institute of Technology, Tokyo, Japan in 1978 and 2003 respectively and the M.S. degree in Electrical Engineering from Princeton University, Princeton, New Jersey, USA in 1987. He joined Semiconductor and Integrated Circuit Group, Hitachi ltd., Tokyo, Japan in 1978, where he was engaged in research and development of state of the art SRAM process and devices. He was also working on developing process technology for LOGIC, embedded memories, and CMOS power RF devices and on transferring technology to mass production line. He invented some of the outstanding structures for SRAM. He pioneered process to implement new materials in mass production, including W-polycide, Al-Cu-Si in 1984 and in-situ phosphorus-doped-polysilicon in 1990. He is the first to realize Lightly Doped Drain (LDD) in production to suppress Hot Carrier Injection in 1984. He also firstly implemented polyimide coat of the chip to immune SER caused by alpha particle from the resin covers the chip. In October 2000, he joined Trecenti Technologies Inc. He developed new process scheme with aggressive reduction of process time and suitable for single-wafer processing. That achieved less than 0.25days/layer cycle time. In April 2005, he joined ATDF at Austin Texas, as a Director of Technology. Where he develops various kinds of technologies includes scaled CMOS, non-classical CMOS, new materials and tools. He established tei Technology LLC in May 2008, Omni Water Solutions LLC, in 2009 at Austin Texas. He started tei Solutions Inc in Tsukuba, Ibaraki, Japan in 2010, where, he manages R&D foundry developing new devices, process technologies for VLSIs. He also integrates emerging technology onto semiconductor manufacturing technology to create innovative products/businesses. Due to his contributions to 200 MHz RISC microprocessor, he got 1999 R&D 100 Award. He served as subcommittee and executive committee member of IEDM from 1993 to 2002. He introduced Manufacturing Session in 1998 and chaired IEDM in 2002. He was a member of EDS Administrative Committee from 2005 to 2010. He was a technical program member for VLSI Technology Symposium in 2007 and 2008. He serves as a chairman of VLSI committee of EDS from 2009 and AdHoc Committee on Asia EDS Conference from 2014. M.Jagadesh Kumar - Senior Member Lecture Topics: 1) Nanowire electronics: the future of CMOS technology 2) Green Transistors for energy efficient integrated circuits 3) Can Bipolar Transistors be made without doping? 4) Tunnel field effect transistors: Design and Optimization 5) Trench power MOSFETs: Design and Optimization 6) Perspectives on the evolution of semiconductor manufacturing: Enabling the impossible Dr. Kumar is currently the NXP (Philips) Chair Professor established at IIT Delhi by Philips Semiconductors, Netherlands (now NXP Semiconductors India Pvt Ltd). He was the Co-ordinator of VLSI Design, Tools and Technology interdisciplinary program. He is a Chief Investigator of the Nano-scale Research Facility (NRF) at IIT Delhi. Dr. Kumar received the 2013 Award for Excellence in Teaching (in large class category) from IIT Delhi. He works in the area of Nanoelectronic Devices, Device modeling and simulation, IC Technology and Power semiconductor devices. He has published extensively in the above areas with four book chapters and more than 160 publications in refereed journals and conferences. He is on the Editorial Board of Scientific Reviews, an online and open access primary research publication from the publishers of Nature. He is an Editor of IEEE Transactions on Electron Devices and the Editor-in-Chief of IETE Technical Review. Dr. Kumar is a Fellow of Indian National Academy of Engineering, The National Academy of Sciences, India, and The Institution of Electronics and Telecommunication Engineers, India. He has been awarded the 29th IETE Ram Lal Wadhwa Gold Medal for distinguished contribution in the field of Semiconductor device design and modeling. He has received the first ever ISA-VSI TechnoMentor Award given by the India Semiconductor Association to recognize a distinguished Indian academician and researcher for playing a significant role as a mentor and researcher. He is a recipient of 2008 IBM Faculty award in recognition of professional achievements. He has delivered a number of invited lectures in conferences and workshops in India and abroad to large audiences on topics related to Nanoelectronics. For more details on Dr. Kumar, you can visit http://web.iitd.ac.in/~mamidala Ming Liu - Senior Member Lecture Topics: nano-fabrication, advanced memory device (charge trap memory, nanocrystal floating gate and resistive switching memory device), nano-electronic device and integrated technology, molecular electronic device and its integration Colin McAndrew Stephan Menzel - Senior Scientist and Group Leader Stephan Menzel received his PhD degree (summa cum laude) from the RWTH Aachen University in 2012. Since 2012, he has been at the Peter Grünberg Institut (PGI-7) at Forschungszentrum Juelich GmbH as senior scienticst. He is now the head of the simulation group at the PGI-7, Forschungszentrum Juelich. His group developed simulation tools for resistive switching devices which are commonly available (www.emrl.de/Jart.html). He is associate editor of Scientific Reports (2015-) and editor of MDPI Materials (2020-). He is listed as golden reviewer for IEEE EDL and IEEE T-ED. He is member of the IEEE since 2012 and member of the EDS and CAS society. He was co-organizer of IEEE NANO 2018 Cork, publication chair of Memrisys 2019 and member of the technical committee of Memrisys 2020. His research interests include the physics, characterization, modeling, and simulation of resistive switching (memristive) devices and computing-in-memory and neuromorphic computing circuits exploiting memristive devices. Stephan Menzel co-authored overall more than 100 papers counting more than 2,500 citations, 8 book chapters and gave 22 invited talks (e.g. at NVMTS, IEEE Nano, ISCAS). Mireille Mouis Arokia Nathan - Fellow Professor Arokia Nathan leads a multi-disciplinary research group whose primary focus is on the heterogeneous integration of materials and processes, sensors, energy harvesting and storage devices pertinent to wearable technologies. Formerly a Chair Professor of Photonic Systems and Displays at the University of Cambridge, he is currently a Bye Fellow and Tutor at Darwin College, University of Cambridge. He has over 600 publications, including 5 books, and more that 110 patents and four spin-off companies. He is a Fellow of IEEE, an IEEE Distinguished Lecturer for EDS and Sensor Council, a Chartered Engineer (UK), Fellow of the Institution of Engineering and Technology (UK). Lecture Topics
Paolo Pavan Unil Perera M.K. Radhakrishnan - Life Senior Member MK Radhakrishnan (M’82, SM’94, LSM’18) is the Founder Director of NanoRel LLP -Technical Consultants providing analysis-based solutions to micro and nano electronic industries for improving reliability of devices. As a researcher in the area of semiconductor device failure physics for more than 35 years, he worked with industries (ST Microelectronic and Philips), research institutions (Institute of Microelectronics, Singapore and Indian Space Research Organization) and in academia with National University of Singapore. As a technical consultant he works with many MNCs and also provides training on device failure analysis & reliability to various Industries, Universities and Research Centres. Lecture Topics: - Circa 70 – Semiconductor Device Progression and Challenges towards Nanoera. - Interface Physics and Analysis Challenges in Silicon Nanodevices - Are the Progressions towards the “Benefit of Humanity”? - A Failure Analyst’s View Susanna Reggiani - Associate Professor Susanna Reggiani is Associate Professor at the Faculty of Engineering of the University of Bologna, Italy. She received the Ph.D. degree in Electrical Engineering from the University of Bologna in 2001. Since 2001 she is with the Department of Electronics and with Advanced Research Center for Electronic Systems (ARCES) of the University of Bologna. Her scientific activity has been devoted to the physics, modeling and characterization of electron devices, with special emphasis on transport models in semiconductors. Since 2007 she has been involved in Projects dealing with the TCAD analysis of power MOSFETs, modeling and characterization of hotcarrier stress degradation, modeling of package influences on high-voltage semiconductor FETs, TCAD study of the reliability of GaN-on-Si HEMTS. She is currently involved in European Projects on the development of physically-based models for SiC-based power devices and Smart Power integrated devices. Krishna Shenai, PhD - Senior Fellow Charles Surya - Optoelectronics Devices Charles Surya received his PhD in Electrical Engineering from the University of Rochester in 1987. From 1987 to 1994 he was associated with the Electrical and Computer Engineering Department of Northeastern University. He joined the Electronic and Information Engineering (EIE) Department in 1994 and remained there since. Professor Surya’s research interests are: optoelectronic materials and devices including MOCVD growth of GaN thin films and the study of GaN-based LEDs and UV detectors; growth of organic-inorganic hybrid perovskite materials and the fabrication of advanced perovskite based photovoltaic cells; and low-frequency noise in electron devices. Presently, Professor Surya is spearheading a collaborative effort between The Hong Kong Polytechnic University and the City of Dongguan, China for the establishment of an R&D Center on the study of photovoltaic materials, devices and systems. He became a full professor of the Department in 2002andsince 2013hewas appointed Clarea Au Endowed Professor in Energy. Professor Surya had served in various administrative posts including Associate Head of the EIE Department (2002-2005), Associate Dean of the Faculty of Engineering (2007 – 2010) and the Acting Dean of the Faculty of Engineering (2010 – 2012) of The Hong Kong Polytechnic University. While serving as the Associate Dean and Acting Dean of the Faculty he was responsible for the implementation of outcome-based approach in the Engineering Faculty. From 2007 – 2013 Professor Surya was the The Hong Kong Polytechnic University representative to the Hong Kong University Grants Council Panel for Outcome-based Education to oversee the implementation of Outcome-based Approach among the Engineering Faculties in Hong Kong. He had been active in EDS and had served in various capacities including conference co-chair and chapter chair in the past. He is presently serving as the Chairman of the Optoelectronic Devices Technical Committee. Sam Vaziri Jing Wang - Director, Device Research Jing Wang obtained his Bachelor’s degree (with the highest honor) in Electronic Engineering from Tsinghua University, China in 2001 and his Ph.D. degree in Electrical and Computer Engineering from Purdue University in 2005. His Ph.D. research, supervised by Prof. Mark Lundstrom, was focused on device physics and simulation of silicon nanowire transistors, exploration of nanoscale MOSFETs, and simulation of high electron mobility transistors. Dr. Wang is currently Director of Device Research at Samsung Semiconductor Inc., San Jose, CA, USA, and his research interests cover compact modeling of advanced logic and memory devices, TCAD simulation and device design, circuit performance benchmark and DTCO, the application of machine learning algorithms in semiconductor R&D and EDA, and neuromorphic computing, etc. From 2005 to 2012, Dr. Wang had worked at the IBM Semiconductor Research and Development Center, Hopewell Junction, NY, as a technical lead of the compact modeling team developing 45/32/28/20nm CMOS technology for the Fishkill ISDA alliance. In 2011, he represented the IBM technology enablement organization in the Common Platform Technology Forum as an invited speaker and panelist. From 2012 to 2014, Dr. Wang was with SuVolta Inc., a semiconductor start-up company, where he had served as Director of the TCAD and compact modeling group developing SuVolta’s proprietary, low-power CMOS technology. Dr. Wang has over 40 peer reviewed publications with more than 2,500 citations and 25 granted US patents. He has served on the Industrial Advisory Board (IAB) for multiple university research programs and is the recipient of several innovation awards. Dr. Wang is a Senior Member of the IEEE and the IEEE Electron Devices Society. Carl-Mikael Zetterling Zhen Zhang - Professor Prof. Zhen Zhang is currently a professor of Solid-State Electronics at Department of Engineering Sciences, the Angstrom laboratory, Uppsala University, Sweden (assistant professors with tenure track 201308-201705; associate professor 201706-201803; full professor 201804-present). Before joining Uppsala University in Aug. 2013, he was a postdoctoral research fellow (2008-2010) and a Research Staff Member at IBM T. J. Watson Research Center (2010-2013), Yorktown Heights, NY, USA. Prof. Zhang received his Ph.D degree from the Royal Institute of Technology (KTH), Sweden in 2008. He got the M.Sc degree at Shanghai Institute of Ceramics, Chinese Academy of Sciences in 2003 and the B.Sc. degree at University of Science and Technology of China (USTC) in 2000. Prof. Zhang was a recipient of the Ingvar Clarsson Award from Swedish Strategic Research Foundation in 2013. He also received a Göran Gustafssons Prize for young researchers and Swedish Research Council (VR) young researcher grant in 2014. He was appointed Wallenberg Academy Fellow (by Knut and Alice Wallenberg Foundation together with the Royal Swedish Academy of Sciences and the Royal Swedish Academy of Engineering Sciences) in 2015 and SSF Future Research Leader (by Swedish Strategic Research Foundation) in 2016.
His current research interest includes advanced nanofabrication technologies, semiconductor nanoelectronics and nanosensors, metal-semiconductor junctions and device-bio interfaces.
J-EDS Editor-in-Chief
DEISJ-EDS Editors
USA
Dept. of Electical Engineering
- Device modelling and circuit simulation
- Interconnect Technology
- Non-volatile memory technology
- Bio-sensors and circuits
NIRC
Professor of Electrical Engineering
Institute of Microelectronics, CAS
- Flexible Electronics
- Oxide Semiconductor Electronics
- Ultralow Power Transistors and Sensor Interfaces
- Active Matrix OLED Displays
- TFT Compact Modeling and Parameter Extraction
- Nanoscale Large Area Electronics
Physics and Astronomy
University of Chicago
Electrical Engineering
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