Editor-in-Chief and Editors

Constantin Bulucea (S'69–M'70–SM'88–F'04- LF'13) was born in Râmnicu Valcea, Romania. In 1969, he got a one-year government scholarship at the University of California, Berkeley, where he received a M.S. degree in Electrical Engineering. In 1974, he received his Doctor degree in Electronis from the Polytechnic Institute of Bucharest with a thesis on hot-carrier injection in silicon. His original results were communicated at IEDM and published in the old (W. Crawford Dunlap’s) Solid-State Electronics. In Romania, he created the Annual Conference on Semiconductors, now an international IEEE event. His best known contribution from that period is the explanation of Grove’s breakdown voltage collapse in silicon gate-controlled devices as a breakdown-location switching phenomenon, as proven by 2-D computer calculations and measurements. Among his “firsts” from the same time is the direct proof, by DC recordings (rather than by capacitive inferences) of nA-range hot-carrier currents through silicon dioxide.

In 1886, Dr. Bulucea defected to the US, where he first developed a device/process architecture for rugged trench power DMOS transistors, while working for Siliconix (1987-1989). His inventive design became a world standard in the following years. Later on, at National Semiconductor (NS), he was a member of the Fairchild Research Center, then joined the company’s process development group. There, he enjoyed the last years of Silicon Valley's "Happy Scaling" as the architect of several CMOS processes for high-performance analog and mixed-signal applications (2000-2010). In 2011, he became a Distinguished Member of the Technical Staff of Texas Instruments (TI), as a result of TI's acquisition of NSC. Throughout his tenure at NS and TI, he received three Patent of the Year awards, in recognition of the use of his inventions in high-volume manufacturing. He has published over 50 technical articles in major journals and has 70 issued US patents. In 2001, he was elected an Honorary Member of the Romanian Academy and in 2004 became an IEEE Fellow "for contributions to transistor engineering in the area of power electronics".

Dr. Bulucea has been a member of the Technical Committees of the Bipolar Circuits and Technology Meeting (BCTM) and of the VLSI Technology Symposium. Between 2004 and 2012 he was the editor of IEEE Electron Device Letters (EDL) for analog and mixed-signals technology. His IEEE responsibilities include membership in the IEEE/EDS Fellow Evaluation Committee (2018, 2019) and the IEEE/EDS Publications Committee (current).

Subhananda Chakrabartir received his M.Sc. and Ph.D. degrees from the Department of Electronic Science, University of Calcutta, Kolkata, India in 1991 and 2000, respectively. He was a Lecturer in the Dept. of Physics, St. Xavier’s College, Kolkata. He has been a Senior Research Fellow with the University of Michigan, Ann Arbor, from2001 to 2005, a Senior Researcher with Dublin City University, Dublin City, Ireland, from 2005 to 2006, and a Senior Researcher (RA2) with the University of Glasgow, Glasgow, U.K., from 2006 to 2007. He joined as an Assistant Professor in the Department of Electrical Engineering, IIT Bombay, Mumbai, India, in 2007.Presently, he is a Professor in the same department. He has extensively researched in molecular beam epitaxial(MBE) growth, characterization, and fabrication of compound (III-V) GaAs-based semiconductor optoelectronic materials and devices, such as intersubband infrared photodetectors etc. He has been the first to demonstrate complete indigenous development Infrared Photodetector based Focal Plane Array in India. In II-VI (ZnO) based research, he has demonstrated stable p-doping through Plasma Immersion Ion Implantation (PIII) technique and subsequently demonstrated a homojunction ZnO-based UV-LED. He is a fellow of the Institution of Electrical and Telecommunication Engineers (IETE) India, Member of the IEEE, MRS USA, SPIE USA etc. He is the medal recipient of the Materials Research Society of India. Recently, he was awarded NASI-Reliance Industries Platinum Jubilee Award for Application Oriented Innovations in Physical Sciences for the year 2016. He has authored more than 200 papers in international journals and conferences. He has also co-authored a couple of book chapters on intersubband quantum dot detectors. His four (4) research monographs with Springer are in press. Dr. S. Chakrabarti has served as reviewer for a number of international journals of repute such as Applied Physics Letters, Nature Scientific Report, IEEE Photonics Technology Letters, IEEE Journal of Quantum Electronics, Journal of Alloys and Compound, Material Research Bulletin etc.

Nadine Collaert received the M.S. and Ph.D. degrees in electrical engineering from the ESAT Department, KU Leuven, Belgium, in 1995 and 2000, respectively. Since then, she has been involved in the theory, design, and technology of FinFET devices, emerging memory devices, transducers for biomedical applications and the integration and characterization of biocompatible materials e.g. carbon-based materials. From 2012 until April 2016 she was program manager of the imec LOGIC program, focusing on high mobility channels, TFET and nanowires. Since April 2016 she is a distinguished member of technical staff, responsible for the research on novel CMOS scaling approaches based on heterogeneous integration of new materials with Si and new material-enabled device and system approaches to increase functionality. She has authored or co-authored more than 300 papers in international journals and conference proceedings, and she holds more than 10 patents in the field of device design and process technology. She has been a member of the CDT committee of the IEDM conference and she is still a member of the Program Committees of the international conferences ESSDERC, ULIS/EUROSOI, NMDC, S3S and the VLSI Technology Symposium.

Lecture Topics: 1) Nanowire electronics: the future of CMOS technology 2) Green Transistors for energy efficient integrated circuits 3) Can Bipolar Transistors be made without doping? 4) Tunnel field effect transistors: Design and Optimization 5) Trench power MOSFETs: Design and Optimization 6) Perspectives on the evolution of semiconductor manufacturing: Enabling the impossible

Dr. Kumar is currently the NXP (Philips) Chair Professor established at IIT Delhi by Philips Semiconductors, Netherlands (now NXP Semiconductors India Pvt Ltd). He was the Co-ordinator of VLSI Design, Tools and Technology interdisciplinary program. He is a Chief Investigator of the Nano-scale Research Facility (NRF) at IIT Delhi. Dr. Kumar received the 2013 Award for Excellence in Teaching (in large class category) from IIT Delhi. He works in the area of Nanoelectronic Devices, Device modeling and simulation, IC Technology and Power semiconductor devices. He has published extensively in the above areas with four book chapters and more than 160 publications in refereed journals and conferences. He is on the Editorial Board of Scientific Reviews, an online and open access primary research publication from the publishers of Nature. He is an Editor of IEEE Transactions on Electron Devices and the Editor-in-Chief of IETE Technical Review. Dr. Kumar is a Fellow of Indian National Academy of Engineering, The National Academy of Sciences, India, and The Institution of Electronics and Telecommunication Engineers, India. He has been awarded the 29th IETE Ram Lal Wadhwa Gold Medal for distinguished contribution in the field of Semiconductor device design and modeling. He has received the first ever ISA-VSI TechnoMentor Award given by the India Semiconductor Association to recognize a distinguished Indian academician and researcher for playing a significant role as a mentor and researcher. He is a recipient of 2008 IBM Faculty award in recognition of professional achievements. He has delivered a number of invited lectures in conferences and workshops in India and abroad to large audiences on topics related to Nanoelectronics. For more details on Dr. Kumar, you can visit http://web.iitd.ac.in/~mamidala

Stephan Menzel received his PhD degree (summa cum laude) from the RWTH Aachen University in 2012. Since 2012, he has been at the Peter Grünberg Institut (PGI-7) at Forschungszentrum Juelich GmbH as senior scienticst. He is now the head of the simulation group at the PGI-7, Forschungszentrum Juelich. His group developed simulation tools for resistive switching devices which are commonly available (www.emrl.de/Jart.html).

He is associate editor of Scientific Reports (2015-) and editor of MDPI Materials (2020-). He is listed as golden reviewer for IEEE EDL and IEEE T-ED.

He is member of the IEEE since 2012 and member of the EDS and CAS society. He was co-organizer of IEEE NANO 2018 Cork, publication chair of Memrisys 2019 and member of the technical committee of Memrisys 2020.

 His research interests include the physics, characterization, modeling, and simulation of resistive switching (memristive) devices and computing-in-memory and neuromorphic computing circuits exploiting memristive devices. Stephan Menzel co-authored overall more than 100 papers counting more than 2,500 citations, 8 book chapters and gave 22 invited talks (e.g. at NVMTS, IEEE Nano, ISCAS).

Susanna Reggiani is Associate Professor at the Faculty of Engineering of the University of Bologna, Italy. She received the Ph.D. degree in Electrical Engineering from the University of Bologna in 2001. Since 2001 she is with the Department of Electronics and with Advanced Research Center for Electronic Systems (ARCES) of the University of Bologna. Her scientific activity has been devoted to the physics, modeling and characterization of electron devices, with special emphasis on transport models in semiconductors. Since 2007 she has been involved in Projects dealing with the TCAD analysis of power MOSFETs, modeling and characterization of hotcarrier stress degradation, modeling of package influences on high-voltage semiconductor FETs, TCAD study of the reliability of GaN-on-Si HEMTS. She is currently involved in European Projects on the development of physically-based models for SiC-based power devices and Smart Power integrated devices.

Jing Wang obtained his Bachelor’s degree (with the highest honor) in Electronic Engineering from Tsinghua University, China in 2001 and his Ph.D. degree in Electrical and Computer Engineering from Purdue University in 2005. His Ph.D. research, supervised by Prof. Mark Lundstrom, was focused on device physics and simulation of silicon nanowire transistors, exploration of nanoscale MOSFETs, and simulation of high electron mobility transistors.

Dr. Wang is currently Director of Device Research at Samsung Semiconductor Inc., San Jose, CA, USA, and his research interests cover compact modeling of advanced logic and memory devices, TCAD simulation and device design, circuit performance benchmark and DTCO, the application of machine learning algorithms in semiconductor R&D and EDA, and neuromorphic computing, etc. From 2005 to 2012, Dr. Wang had worked at the IBM Semiconductor Research and Development Center, Hopewell Junction, NY, as a technical lead of the compact modeling team developing 45/32/28/20nm CMOS technology for the Fishkill ISDA alliance. In 2011, he represented the IBM technology enablement organization in the Common Platform Technology Forum as an invited speaker and panelist. From 2012 to 2014, Dr. Wang was with SuVolta Inc., a semiconductor start-up company, where he had served as Director of the TCAD and compact modeling group developing SuVolta’s proprietary, low-power CMOS technology.

Dr. Wang has over 40 peer reviewed publications with more than 2,500 citations and 25 granted US patents. He has served on the Industrial Advisory Board (IAB) for multiple university research programs and is the recipient of several innovation awards. Dr. Wang is a Senior Member of the IEEE and the IEEE Electron Devices Society.