Lastest Issue: Table of Contents (TOC)
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- Analytical Modeling of Exposure Process in Pinned Photodiode CMOS Image Sensors
- A Temperature Compensation Method by Adjusting Gamma Voltages for High Luminance Uniformity of Active Matrix Organic Light-Emitting Diode Displays
- Al0.75Ga0.25N/AlxGa1-xN/Al0.75Ga0.25N/AlN/SiC MetalOxideSemiconductor Heterostructure Field-Effect Transistors With Symmetrically-Graded Widegap Channel
- High-
${k}$ - Analysis and Modeling of Lateral Power Devices With Stepped Drift Region Thickness via Effective Concentration Profile Concept
- Fabrication of CMOS Invertors in Si Thin-Film-Transistors by Laser Doping Using a Chemical Solution Coating
- Computational Modelling-Based Device Design for Improved mmWave Performance and Linearity of GaN HEMTs
- Superjunction Power Transistors With Interface Charges: A Case Study for GaN
- An Analytical Breakdown Model for the SOI LDMOS With Arbitrary Drift Doping Profile by Using Effective Substrate Voltage Method
- An Improved iMemComp OR Gate and its Applications in Logic Circuits
- Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory
- Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs
- Reverse Leakage Analysis for As-Grown and Regrown Vertical GaN-on-GaN Schottky Barrier Diodes
- An Enhanced Floating Gate Memory for the Online Training of Analog Neural Networks
- Comprehensive Studies of High-Linearity Position-Sensitivity Detectors With Theoretical Consideration on Lateral Photovoltaic Currents
- First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State
- Investigation of Inversion Charge Characteristics and Inversion Charge Loss for InGaAs Negative-Capacitance Double-Gate FinFETs Considering Quantum Capacitance
- Enhanced Switching Properties in TaOx Memristors Using Diffusion Limiting Layer for Synaptic Learning
- A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 C
- High-Frequency Characteristics of InGaP/GaAs Double Heterojunction Bipolar Transistor Epitaxially Grown on 200 mm Ge/Si Wafers
- 1/
${f}^{gamma}$ - Thermal Analysis of AlGaN/GaN Hetero-Structural Gunn Diodes on Different Substrates Through Numerical Simulation
- Analysis and Optimization of Threshold Voltage Variability by Polysilicon Grain Size Simulation in 3D NAND Flash Memory
- Trap Analysis Based on Low-Frequency Noise for SiC Power MOSFETs Under Repetitive Short-Circuit Stress
- Low-Voltage Hf-ZnO Thin Film Transistors With Ag Nanowires Gate Electrode and Their Application in Logic Circuit
- Rail-to-Rail Timing Signals Generation Using InGaZnO TFTs For Flexible X-Ray Detector
- Size-Dependent Switching Properties of Spin-Orbit Torque MRAM With Manufacturing-Friendly 8-Inch Wafer-Level Uniformity
- Erratum to Comprehensive Studies of High-Linearity Position-Sensitivity Detectors With Theoretical Consideration on Lateral Photovoltaic Currents [Jan 20 92-98]
- A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
- An Efficient Design Approach to Optimize the Drift Layer of Unipolar Power Devices in 4H-SiC
- NCFET-Based 6-T SRAM: Yield Estimation Based on Variation-Aware Sensitivity
- A Mobility Model Considering Temperature and Contact Resistance in Organic Thin-Film Transistors
- Trench Shielded Planar Gate IGBT (TSPG-IGBT) With Self-Biased pMOS Realizing Both Low On-State Voltage and Low Saturation Current
- Collaborative Applying the Ultra-low-k Dielectric and the High-k Dielectric Materials for Performance Enhancement in Coupled Multilayer Graphene Nanoribbon Interconnects
- Extension of the DG Model to the Second-Order Quantum Correction for Analysis of the Single-Charge Effect in Sub-10-nm MOS Devices
- 1.6-kV 1.5-kA GaAs Avalanche Semiconductor Switch Triggered by 4 J Laser Diode
- Normally-off p-GaN Gated AlGaN/GaN HEMTs Using Plasma Oxidation Technique in Access Region
- Pixel Circuit With Leakage Prevention Scheme for Low-Frame-Rate AMOLED Displays
- Design and Optimization of Vertical GaN PiN Diodes With Fluorine-Implanted Termination
- Process Integration and Interconnection Design of Passive-Matrix LED Micro-Displays With 256 Pixel-Per-Inch Resolution
- Effective Concentration Profile: A Novel 1-D Analysis of the Variation of Lateral Thickness (VLT) Lateral Power Devices
- Characterization and Modeling of Mismatch in Cryo-CMOS
- A Compact Model of MoS2 Field-Effect Transistors From Drift-Diffusion to Ballistic Carrier Transport Regimes
- Current Pulses to Control the Conductance in RRAM Devices
- Schottky Barrier Height Engineering in
-Ga2O3 Using SiO2 Interlayer Dielectric - A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond
- Low-Leakage Capacitive Coupling Structure for a-Si:H Gate Driver With Less Delay of Clock Signals Used in AMLCDs
- Impact of Source to Drain Tunneling on the Ballistic Performance of Si, Ge, GaSb, and GeSn Nanowire p-MOSFETs
- 1.4-kV Quasi-Vertical GaN Schottky Barrier Diode With Reverse
p-n Junction Termination - Analysis on Temperature Dependence of Hot Carrier Degradation by Mechanism Separation
- Decreased Motion Blur in Large-Size, Organic, Light-Emitting Device Panels Due to Integrated Gate Driver Circuits With a Moving-Picture Response-Time-Reduction Method
- Effect of Substrate Choice on Transient Performance of Lateral GaN FETs
- Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current
- Improvement in Electrical Characteristics of ZnSnO/Si Bilayer TFET by W/AlO Gate Stack
- An AlGaN/GaN High Electron Mobility Transistor With a Built-In Light Emitter Using Radiative Recombination of Two-Dimensional Electron Gas and Holes
- Traps Around Ge Schottky Junction Interface: Quantitative Characterization and Impact on the Electrical Properties of Ge MOS Devices
- Investigation of SiN
x and AlN Passivation for AlGaN/GaN High-Electron-Mobility Transistors: Role of Interface Traps and Polarization Charges - Energy-Delay Sensitivity Analysis of a Nanoelectromechanical Relay With the Negative Capacitance of a Ferroelectric Capacitor
- Foreword
- Simulation of CMOS APS Operation and Crosstalk in SPICE With Generalized Devices
- DC and 28 GHz Reliability of a SOI FET Technology
- Origin of the Negative Differential Resistance in the Output Characteristics of a Picene-Based Thin-Film Transistor
- Charge-Based Compact Modeling of Capacitances in Staggered Multi-Finger OTFTs
- Parameter Extraction and Compact Modeling of 1/f Noise for Amorphous ESL IGZO TFTs
- Inverted Polymer Solar Cells Using Inkjet Printed ZnO as Electron Transport Layer: Characterization and Degradation Study
- Effects of Annealing Temperature on the Performance of Organic Solar Cells Based on Polymer: Non-Fullerene Using V2O5 as HTL
- Physical Mechanisms of Reverse DIBL and NDR in FeFETs With Steep Subthreshold Swing
- Dimension Scaling Effects on Conduction and Low Frequency Noise Characteristics of ITO-Stabilized ZnO Thin Film Transistors
- Thermal Field Analysis for New AlGaN/GaN HEMT With Partial Etched AlGaN Layer
- Characterization and Analysis of On-Chip Microwave Passive Components at Cryogenic Temperatures
- The Dependence of the High-Frequency Performance of Graphene Field-Effect Transistors on Channel Transport Properties
- Reset Variability in Backfilled Resistive Random Access Memory and Its Correlation to Low Frequency Noise in Read
- Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter
- High
fmax LG Product of AlGaN/GaN HEMTs on Silicon With Thick Rectangular Gate - Performance Investigation of an n-Type Tin-Oxide Thin Film Transistor by Channel Plasma Processing
- Photo-Controlled Quantum Capacitors in Gated Graphene-Insulator-Graphene for Terahertz Frequency and Phase Modulations
- 2.3 kV 4H-SiC Accumulation-Channel Split-Gate Planar Power MOSFETs With Reduced Gate Charge
- Comprehensive n- and pMOSFET Channel Material Benchmarking and Analysis of CMOS Performance Metrics Considering Quantum Transport and Carrier Scattering Effects
- Improvement in Bias Stability of IGZO TFT With Etching Stop Structure by UV Irradiation Treatment of Active Layer Island
- RESURF Principle in AlGaN/GaN HEMTs: Accurate 1-D Modeling on Off-State Avalanche Breakdown Behavior via Effective Concentration Profile
- Oxygen-Related Reliability of Amorphous InGaZnO Thin Film Transistors
- A Compact Model for SiC Schottky Barrier Diodes Based on the Fundamental Current Mechanisms
- Optimization on Adhesive Stamp Mass-Transfer of Micro-LEDs With Support Vector Machine Model
- Novel Power MOSFET With Partial SiC/Si Heterojunction to Improve Breakdown Voltage by Breakdown Point Transfer (BPT) Terminal Technology
- On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs
- Impact of the Crystal Phase of ZrO on Charge Trapping Memtransistor as Synaptic Device for Neural Network Application
- Ultra-Fast (ns-Scale) Characterization of NBTI Behaviors in Si pFinFETs
- Low-Voltage High-Speed Ring Oscillator With a-InGaZnO TFTs
- Germanium Twin-Transistor Nonvolatile Memory With FinFET Structure
- A Novel Shielded IGBT (SIGBT) With Integrated Diodes
- Surface Improvement of InAlAs/InGaAs InP-Based HEMT Through Treatments of UV/Ozone and TMAH
- Device Design Guideline for HfO-Based Ferroelectric-Gated Nanoelectromechanical System
- Schottky Barrier Height Analysis of Diamond SPIND Using High Temperature Operation up to 873 K
- SiC Planar MOSFETs With Built-In Reverse MOS-Channel Diode for Enhanced Performance
- Luminance Compensation and Optimization to Delay OLED Degradation Based on Equivalent Lifetime Detection
- A Novel Low Dynamic Resistance Dual-Directional SCR With High Holding Voltage for 12 V Applications
- MEMS-Based Planar Incandescent Microfilaments With Low Voltage Operation
- Introduction to the Special Section on the 2019 IEEE S3S Conference
- 28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K
- Design and Analysis of a 28GHz 9KV ESD-Protected Distributed Travelling-Wave TRx Switch in 22nm FDSOI
- Energy Filtering Effect at Source Contact on Ultra-Scaled MOSFETs
- A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options Done by Virtual Fabrication
- Materials Requirements of High-Speed and Low-Power Spin-Orbit-Torque Magnetic Random-Access Memory
- Self-Clamping Programming in Narrow-Bridge Floating Gate Cells for Multi-Level Logic Non-Volatile Memory Applications
- Unified Analytical Model for SOI LDMOS With Electric Field Modulation
- Analog IGZO Memristor With Extended Capabilities
- Optical and Electrical Analysis of Core-Shell ZnO/ZnTe Micropillar Solar Cells
- Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications
- Correction to Stable Operation of AlGaN/GaN HEMTs for 25 Hours at 400C in Air
- Low-Voltage Operating Ferroelectric FET with Ultrathin IGZO Channel for High-Density Memory Application
- Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor
- Mechanism of AlGaAs/InGaAs pHEMT Nonlinear Response Under High-Power Microwave Radiation
- Guest Editorial
- Inherent Charge-Sharing-Free Dynamic Logic Gates Employing Transistors With Multiple Independent Inputs
- Compact FeFET Circuit Building Blocks for Fast and Efficient Nonvolatile Logic-in-Memory
- Smart Logic-in-Memory Architecture for Low-Power Non-Von Neumann Computing
- Performance and Reliability Degradation of CMOS Image Sensors in Back-Side Illuminated Configuration
- Monolithically Integrated Catalyst-Free High Aspect Ratio InAs-on-Insulator (InAsOI) FinFETs for pH Sensing
- Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs
- Self-Heating in FDSOI UTBB MOSFETs at Cryogenic Temperatures and its Effect on Analog Figures of Merit
- Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures
- Enhancement of Room-Temperature Effective Spin Diffusion Length in a Si-Based Spin MOSFET With an Inversion Channel
- Parameter Extraction for the PSPHV LDMOS Transistor Model
- Edge-Etched Al2O3 Dielectric as Charge Storage Region in a Coupled MIS Tunnel Diode Sensor
- A Quantum-Well Charge-Trap Synaptic Transistor With Highly Linear Weight Tunability
- Different JFET Designs on Conduction and Short-Circuit Capability for 3.3 kV Planar-Gate Silicon Carbide MOSFETs
- The Impact of Channel Semiconductor on the Memory Characteristics of Ferroelectric Field-Effect Transistors
- Comparative Study on Dynamic Characteristics of GaN HEMT at 300K and 150K
- Vertical GaN-on-GaN Schottky Barrier Diodes With Multi-Floating Metal Rings
- ESD Improvements on Power N-Channel LDMOS Devices by the Composite Structure of Super Junctions Integrated With SCRs in the Drain Side
- Design and Simulation of High Performance Lattice Matched Double Barrier Normally Off AlInGaN/GaN HEMTs
- Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors
- Temperature Gradient ZnO Deposited via ALD for High-Performance Transistor Applications
- Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance
- Characterization and Modeling of 0.18
m Bulk CMOS Technology at Sub-Kelvin Temperature - A Fast Extraction Method of Energy Distribution of Border Traps in AlGaN/GaN MIS-HEMT
- Experimental Research of X-Band Dual-Frequency Coaxial Relativistic Backward Wave Oscillator
- Novel Green Temporary Bonding and Separation Method for Manufacturing Thin Displays
- GaN Nanotube FET With Embedded Gate for High Performance, Low Power Applications
- In.Ga.As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz
f and 256 GHzf max - Dual-Storage-Port Nonvolatile SRAM Based on Back-End-of-the-Line Processed Hf0.5Zr0.5O Ferroelectric Capacitors Towards 3D Selector-Free Cross-Point Memory
- Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect
- Physical Modeling of
p -Type Fluorinated Al-Doped Tin-Oxide Thin Film Transistors - Substrate Engineering of Inductors on SOI for Improvement of Q-Factor and Application in LNA
- Impact of Surface Treatments and Post-Deposition Annealing Upon Interfacial Property of ALD-AlO on a-Plane GaN
- A Novel High Schottky Barrier Based Bilateral Gate and Assistant Gate Controlled Bidirectional Tunnel Field Effect Transistor
- Realization of Synapse Behaviors Based on Memristor and Simulation Study With KMC Method
- Thermal Modeling of GaN HEMT Devices With Diamond Heat-Spreader
- TCAD-Machine Learning Framework for Device Variation and Operating Temperature Analysis With Experimental Demonstration
- Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors
- Low Turn-Off Loss 4H-SiC Insulated Gate Bipolar Transistor With a Trench Heterojunction Collector
- Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio
- Hydrogen Source and Diffusion Path for Poly-Si Channel Passivation in Xtacking 3D NAND Flash Memory
- Study on the IGBT Using a Deep Trench Filled With SiO2 and High-k Dielectric Film
- Analytical Study on the Breakdown Characteristics of Si-Substrated AlGaN/GaN HEMTs With Field Plates
- Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node
- Modeling the Displacement Damage on Trigger Current of Anode-Short MOS-Controlled Thyristor
- An Improved Self-Powered H-Bridge Circuit for Voltage Rectification of Piezoelectric Energy Harvesting System
- Investigation of THz Frequency Shaped Anode Planar Gunn Diodes Operating in Delayed Mode
- Impact of Series-Connected Ferroelectric Capacitor in HfO-Based Ferroelectric Field-Effect Transistors for Memory Application
- Simulation Study on Dynamic and Static Characteristics of Novel SiC Gate-Controlled Bipolar-Field-Effect Composite Transistor
- Realization of an IGBT Gate Driver With Dualphase Turn-On/Off Gate Control
- Ionization Damage Effects of Pulse Discharge Circuit Switched by Anode-Short MOS-Controlled Thyristor
- Foreword Special Issue From the Selected Extended Papers Presented at EDTM 2020
- Third Generation PRESiCE Technology for Manufacturing SiC Power Devices in a 6-Inch Commercial Foundry
- Performance Modeling of Silicon Carbide Photoconductive Switches for High-Power and High-Frequency Applications
- Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design
- Quasi-Normally-Off AlGaN/GaN HEMTs With SiN Stress Liner and Comb Gate for Power Electronics Applications
- Efficient Modeling of Barrier Resistance for an Improved Lumped Element Model of GaN-Based MIS-HEMT Gate Stack
- Effect of Nanostructure on Carrier Transport Mechanism of III-Nitride and Kesterite Solar Cells: A Computational Analysis
- Indium Silicon Oxide TFT Fully Photolithographically Processed for Circuit Integration
- Compact Modeling of Surface Potential, Drain Current and Terminal Charges in Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport
- Compact Modeling of Multi-Layered MoS2 FETs Including Negative Capacitance Effect
- Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS
- Impact of Interface Traps on Negative Capacitance Transistor: Device and Circuit Reliability
- Heterostructure Ge-Body pTFETs for Analog/RF Applications
- A CMOS Low Power Current Source Tunable Inductor With 80 Tuning Range for RFIC
- Printable Low Power Organic Transistor Technology for Customizable Hybrid Integration Towards Internet of Everything
- Multilayer CVD-Graphene and MoS Ethanol Sensing and Characterization Using Kretschmann-Based SPR
- Subthreshold Operation of Photodiode-Gated Transistors Enabling High-Gain Optical Sensing and Imaging Applications
- Under-FET Thermal Sensor Enabling Smart Full-Chip Run-Time Thermal Management
- Analysis of Switching Under Fixed Voltage and Fixed Current in Perpendicular STT-MRAM
- A Unified Memory and Hardware Security Module Based on the Adjustable Switching Window of Resistive Memory
- Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks
- Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications
- Modeling of DC - AC NBTI Stress - Recovery Time Kinetics in P-Channel Planar Bulk and FDSOI MOSFETs and FinFETs
- 3D TCAD Analysis Enabling ESD Layout Design Optimization
- Pad-Based CDM ESD Protection Methods Are Faulty
- Understanding and Improving Reliability for Wafer Level Chip Scale Package: A Study Based on 45nm RFSOI Technology for 5G Applications
- Note Clarifying the Paper, Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design
- Asymmetric Low Metal Contamination Ni-Induced Lateral Crystallization Polycrystalline-Silicon Thin-Film Transistors With Low OFF-State Currents for Back-End of Line (BEOL) Compatible Devices Applications
- 3D Simulation for Melt Laser Anneal Integration in FinFETs Contact
- Using the MSET Device to Counteract Power-Analysis Attacks
- Simulative Researching of a 1200V SiC Trench MOSFET With an Enhanced Vertical RESURF Effect
- Enhanced Non-Uniformity Modeling of 4H-SiC Schottky Diode Characteristics Over Wide High Temperature and Forward Bias Ranges
- Methodology to Investigate Impact of Grain Orientation on Threshold Voltage and Current Variability in Tunneling Field-Effect Transistors
- CFP Special issue on Compact Modeling
