Editor-in-Chief and Editors

Giovanni Ghione graduated cum laude in Electronic Engineering from Politecnico di Torino, Torino Italy in 1981. He was Assistant Professor in Electromagnetic Fields since 1983, Associate Professor in Circuit Theory with Politecnico di Milano, Milano Italy since 1987, and finally Full Professor in Electronics since 1990, first with University of Catania, then again with Politecnico di Torino. His research activity has been mainly concerned with high-frequency electronics and optoelectronics. He has contributed to the physics-based modelling of compound semiconductor devices, with particular interest in the numerical noise modeling in the small- and large-signal regimes, in the thermal modeling of devices and integrated circuits, and in the modeling of widegap semiconductors devices and materials. He has also done research in the field of microwave electronics, with contributions in the modeling of passive elements, in particular coplanar components, and in the design of power MMICs. Prof. Ghione was actively engaged since 1985 in research on optoelectronic devices, with application to the modeling and design of near and far-IR photodetectors, electrooptic and electroabsorption modulators, and GAN-based LEDs. Prof. Ghione has authored or co-authored more than 300 research papers on the above subjects and five books. He is an IEEE Fellow (class 2007). He has been a member of the QPC subcommitee of IEDM in 1997-1998 and in 2006-2007 and Chair in 2008; in 2009-2010 he was the EU Arrangement Co-Chair of IEDM. From 2010 to 2015 he has been chair of the EDS Committee on Compound Semiconductor Devices and Circuits. He has been Chair of the GAAS2003 conference and he has been subcommittee chair in several SCs of the European Microwave Week. He was President of the Library System of Politecnico from 1997 to 2007. From 2007 to 2015 he was the Head of the Department of Electronics and Telecommunications of Politecnico di Torino.

Uygar E. Avci received double-major BS degrees in Physics and Electrical Engineering from Bogazici University, Istanbul, Turkey in 1999 and was the recipient of the President’s Award. He received his MS and PhD degrees in Applied Physics from Cornell University, Ithaca, NY in 2003 and 2005, respectively. During his doctorate study, he demonstrated the first experimental realization of back-side flash memory. He joined Intel’s Components Research in 2005, leading Floating Body Cell (FBC) memory experimental device design and scaling that demonstrated industry-leading FBC memory cells. Since 2010, he has focused on the opportunities that beyond-CMOS devices offer to either replace or augment CMOS. He has defined Tunnel-FET device and material options, its scaling roadmap and the road blocks by bridging Physics-based models with experimental material realities. His research includes circuit evaluation of novel devices comprehending the parasitics, interconnect and density to explore their potential for future products. He is currently a Principle Engineer, leading the research for charge-based beyond-CMOS devices and circuits in Intel’s Components Research department. Dr. Avci served as the Fundamentals Class Chair and the Short Course Chair for the International SOI Conference, in 2012 and 2013, respectively. He has ten filed patents and published twenty-nine papers in international conferences and journals.

Muhannad S. Bakir received the B.E.E. degree (summa cum laude) from Auburn University, Auburn, AL, in 1999 and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology (Georgia Tech) in 2000 and 2003, respectively. He is currently an Associate Professor and the ON Semiconductor Junior Professor in the School of Electrical and Computer Engineering at Georgia Tech. His areas of interest include three-dimensional (3D) electronic systems, advanced interconnection and packaging, and nanofabrication technology. He is the co-editor (with James D. Meindl) of a book entitled Integrated Interconnect Technologies for 3D Nanoelectronic Systems (Artech House, 2009) and is the author/coauthor of more than 110 journal publications and conference proceedings, 14 US patents, and the presenter of 2 conference tutorials, including an invited tutorial on 3D technology at the 2007 International Solid-State Circuits Conference (ISSCC). Dr. Bakir is the recipient of the 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, 2011 IEEE CPMT Society Outstanding Young Engineer Award, and was an Invited Participant in the 2012 National Academy of Engineering Frontiers of Engineering Symposium. He is also a recipient of the Semiconductor Research Corporation (SRC) Inventor Recognition Awards (2002, 2005, 2009). Dr. Bakir also received twelve conference and student paper awards including one from the IEEE Custom Integrated Circuits Conference (CICC), five from the IEEE Electronic Components and Technology Conference (ECTC), and three from the IEEE International Interconnect Technology Conference (IITC). Dr. Bakir an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology, and was a Guest Editor of the June 2011 Special Issue of IEEE Journal of Selected Topics in Quantum Electronics. He is also a member of the International Technology Roadmap for Semiconductors (ITRS) technical working group for Assembly and Packaging (AP).

Richard G. Carter graduated in physics from the University of Cambridge in 1965 and received his PhD in electronic engineering from the University of Wales in 1968. From 1968 to 1972 he worked on high power travelling-wave tubes as a Development Engineer at English Electric Valve Co. Ltd.. He joined the Engineering Department of the University of Lancaster as a Lecturer in 1972 and was promoted to Senior Lecturer in 1986 and Professor of Electronic Engineering in 1996. He became an Emeritus Professor on his retirement in 2009. His research interests include electromagnetics and microwave engineering with particular reference to the theory, design and computer modelling of microwave tubes and particle accelerators. He is the author of two books and numerous papers in the field. He is currently working on a book entitled 'Microwave and RF Vacuum Electronic Power Sources' to be published by Cambridge University Press in 2018. Professor Carter is a Fellow of the IET, a Senior Member of IEEE and was a member of the Vacuum Electronics Technical Committee of the IEEE Electron Devices Society from 1998 to 2015. He received the IVEC 2009 Award for Excellence in Vacuum Electronics for ‘a life-long commitment to education in vacuum electronics and visionary leadership in academia and technical research in the field’. He has been an editor for T-ED since 2011.

Talk titles:

·        Modeling and Simulation of Negative Capacitance Transistors

·        Compact Modeling of GaN HEMTs using industry standard ASM-HEMT model

·        Physics and Modeling of FinFET and Nanosheet Transistors

·        Analog and RF Modeling in BSIM-BULK model

·        Physics and Modeling of FDSOI Transistors

Yogesh Singh Chauhan is an associate professor at Indian Institute of Technology Kanpur (IITK), India. He was with Semiconductor Research & Development Center at IBM Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; University of California Berkeley during 2010-2012; and ST Microelectronics during 2003-2004. He is the developer of several industry standard models: ASM-GaN-HEMT model, BSIM-BULK model (formerly BSIM6), BSIM-CMG model and BSIM-IMG model. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs. His research interests are characterization, modeling, and simulation of semiconductor devices.

            He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the member of IEEE-EDS Compact Modeling Committee and fellow of Indian National Young Academy of Science (INYAS). He is the founding chairperson of IEEE Electron Devices Society U.P. chapter and Vice-chairperson of IEEE U.P. section. He has published more than 200 papers in international journals and conferences.

            He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award, Humboldt fellowship and Swarnajayanti fellowship in 2018. He has served in the technical program committees of IEEE International Electron Devices Meeting (IEDM), IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), IEEE European Solid-State Device Research Conference (ESSDERC), IEEE Electron Devices Technology and Manufacturing (EDTM), and IEEE International Conference on VLSI Design and International Conference on Embedded Systems.

Kyung Cheol Choi received the B.S. degree from the Department of Electrical Engineering, Seoul National University, Seoul Korea, in 1986, and the M.S. degree and Ph.D. degree in plasma engineering from Seoul National University in 1988 and 1993, respectively. From 1993 to 1999, he was involved with researching and developing display devices at the Institute for Advanced Engineering, Spectron Corporation of America, and Hyundai Electronics Industries. From 2000 to 2004, he was an Associate Professor with the Department of Electronics Engineering, Sejong University, Seoul, Republic of Korea. He was also in charge of the Information Display Research Center supported by the Korean Ministry of Information and Communication. Since February 1, 2005, he has been with the Department of Electrical Engineering, KAIST, Daejeon, Korea, where he was first an Associate Professor and is currently a KAIST Chair Professor. Since September 2007, he has been in charge of the Center for Advanced Flexible Display Convergence supported by the Korean Ministry of Education, Science, and Technology. He has also been in charge of LG Display –KAIST Cooperation center since 2010. His research interests include flexible and transparent displays, organic light-emitting diodes, and surface plasmon applications for electronic devices and displays. Dr. Choi is a member of the IEEE, the Society for Information Display, and the Korean Information Display Society. He had been an Associate Editor of IEEE/OSA Journal of Display Technology from 2005 to 2010.

Lecture Topics: ESD and Latchup Reliability

Elena Gnani received the M.S. degree in Electrical Engineering "summa cum laude" and the Ph.D degree in Electrical Engineering and Computer Science in 2003 with a dissertation entitled "Physical models for MOS nanostructures", both from the University of Bologna. She joined the Department of Electrical, Electronic and Information Engineering at the University of Bologna in 2004, where she is currently Associate Professor. Her research interests include the development of physical transport models in semiconductor devices and numerical-analysis techniques, with special emphasis on the study of quantum-confined devices, such as FinFETs, silicon nanowires (NW), steep-slope devices, quasi ballistic transport in nanoMOSFETs, as well as carrier injection in non-volatile memory cells. She has been involved in several National and European Projects. Her research activities have been carried out in cooperation with worldwide semiconductor research centers and semiconductor industries. E. Gnani is author or co-author of more than 180 papers published in referred international journals and in proceedings of major international conferences, and of several invited contributions, and has been involved in outstanding conferences such as IEDM, DATE, ESSDERC, EUROSOI-ULIS. She has been a member of the IEEE Electron Devices Society (EDS) from 2001, and is presently an IEEE Senior Member and EDS Distinguished Lecturer for Region8. She is also a member of the EDS Technology Computer Aided Design Committee and serves as an associate editor of the IEEE Transactions on Electron Devices.

Lecture Topics:
- Trends and Challenges in Nanoelectronics for the Next Decade
- Steep-slope devices: prospects and challenges
- Theoretical Analyses and Modeling for Nanoelectronics
- Tunnel FETs: Device Physics and Realizations

Prof. Tibor Grasser is an IEEE Fellow and currently head of the Institute for Microelectronics at TU Wien. He has edited various books, e.g. on the bias temperature instability and hot carrier degradation (both Springer), is a distinguished lecturer of the IEEE EDS, has been involved in outstanding conferences such as IEDM, IRPS, SISPAD, ESSDERC, and IIRW, is a recipient of the Best and Outstanding Paper Awards at IRPS (2008, 2010, 2012, and 2014), IPFA (2013 and 2014), ESREF (2008) and the IEEE EDS Paul Rappaport Award (2011).

 

Lecture Topics:

- Semiconductor device reliability (bias temperature instability, hot carrier degradation)
- Noise (RTN, 1/f)
- 2D devices (defects, hysteresis, drifts)

Dr. Edmundo A. Gutiérrez-D. got his PhD in 1993 from the Catholic University of Leuven, Belgium with the thesis entitled “Electrical performance of submicron CMOS technologies from 300 K to 4.2 K”. From 1989 to 1993, while working for his PhD, served as a research assistant at the Interuniversity Microelectronics Center (IMEC) in Leuven, Belgium. In 1996 was guest Professor at Simon Fraser University, Vancouver, Canada. In 1996 spent two months as an invited lecturer at the Sao Paulo University, Brazil. In 2000 acted as Design Manager of the Motorola Mexico Center for Semiconductor Technology. In 2002 was invited lecturer at the Technical University of Vienna, Austria. In 2005 joined the Intel Mexico Research Center as technical Director. Currently he holds a Professor position at the National Institute for Astrophysics, Optics and Electronics (INAOE), in Puebla, Mexico. Prof. Gutiérrez-D. is an IEEE senior member since 2008. Professor Gutiérrez-D. has published over 100 scientific publications and conferences in the field of semiconductor device physics, has supervised 5 M.Sc. and 10 Ph.D. thesis, and is author of the book “Low Temperature Electronics, Physics, Devices, Circuits and Applications” published by Academic Press in 2000. Prof. Gutiérrez-D. is member of the Mexico National System of Researchers and technical reviewer for the Mexico National Council for Science and Technology (CONACyT).

 

Lecture Topics:

-Semiconductor device physics, characterization, and modeling

-Cryogenic electron devices physics, sensors, and systems

-Electro-thermal modeling and thermo-magnetics effects

-Degradation and reliability of advanced FET technologies

Benjamin Iñiguez obtained the Ph D in Physics in 1992 and 1996, respectively, from the Universitat de les Illes Balears (UIB). From February 1997 to September 1998 he was working as a Postdoctoral Researcher at the Rensselaer Polytecnhnic Institute in Troy (NY, USA). From September 1998 to January 2001 he was working as a Postdoctoral Scientist in the Université catholique de Louvain (Louvain-la-Neuve, Belgium), supported by two Marie Curie Fellowships from the European Commission. In February 2001 he joined the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA)of the Universitat Rovira i Virgili (URV), in Tarragona, Catalonia, Spain) as Titular Professor. In February 2010 he became Full Professor at URV. He obtained the Distinction from the Generalitat for the Promotion of University Research in 2004 and the ICREA Academia Award (the highest award for university professors in Catalonia, from ICREA Institute) in 2009 and 2014, for a period of 5 years each. He led one EU-funded project (“COMON”, 2008-12) devoted to the compact modeling of nanoscale semiconductor devices and he is currently leading one new EU-funded project (DOMINO, 2014-18) targeting the compact modeling of organic and oxide TFTs. His main research interests are the characterization, parameter extraction and compact modelling of emerging semiconductor devices, in particularorganic and oxide Thin-Film Transistors, nanoscale Multi-Gate MOSFETs and GaN HEMTs. He has published more than 150 research papers in international journals and more than 130 abstracts in proceedings of conferences.

 

Lecture Topics

Compact device modeling
Semiconductor device parameter extraction
Physics of Thin-Film Transistors
Graphene and TMD devices

Karol Kalna received M.Sc. degree (Hons.) in Solid State Physics in 1990 and Ph.D. degree in Condensed Matter Physics in 1998 from Comenius University, Bratislava, Czechoslovakia. In 1994, he joined Institute of Electrical Engineering, Bratislava, Slovakia, as a Research Scientist. He was a visiting postgraduate student in the Department of Physics, UIA University of Antwerp, Belgium, in 1994 and 1997, working on semiconductor lasers modelling. From 1999 till 2010, he was in the Department of Electronics & Electrical Engineering, University of Glasgow, U. K., where he was studying the scaling of high electron mobility transistor (HEMT) into sub-100 nm dimensions performing DC and RF analysis within ensemble Monte Carlo simulations. From 2002, he pioneered III-V MOSFETs for future digital technology studying transistor scaling with Monte Carlo simulations. From 2007 till 2012, he was an Engineering and Physical Sciences Research Council (EPSRC) Advanced Research Fellow carrying out the Monte Carlo modelling of deep sub-100 nm, ultra-thin body transistors with Si and high mobility materials in a channel. He was involved in several research projects on III-V MOSFETs for digital applications funded by ESPRC and European Community (DualLogic). In 2010, he became a Senior Lecturer and, in 2013, Associated Professor in College of Engineering, Swansea University, Wales, U. K., establishing his own Nanoelectronic Devices Computational Group. He has more than 200 publications including 81 papers in peer-review journals, 3 book chapters and more than 20 invited talks. He is a Senior Member of the IEEE. His research interests include finite element 2D and 3D Monte Carlo simulations of nanoscaled MOSFETs including FinFETs and gate-all-around nanowires with a channel based on Si, strain Si, and III-V semiconductors; quantum transport simulations using Non-Equilibrium Green's Functions; multiscale modelling coupling density functional theory calculations with Monte Carlo simulations; and simulations of GaN based HEMTs and ZnO nanowires.

Dr. Brajesh Kumar Kaushik (S’07–M’09–SM’13) received his Ph.D. degree in 2007 from Indian Institute of Technology Roorkee, India. He joined Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee, as Assistant Professor in December 2009; and since April 2014 he has been working as an Associate Professor. He has authored and reviewed several research publications in renowned journals, national and international conferences. He is a Senior Member of IEEE and holds the position of Editor and Editor-in-Chief of various journals in the field of VLSI and microelectronics. He has received many awards for his significant contribution to the scientific community. His research interests include spintronics-based devices and circuits, high-speed interconnects low-power VLSI design, memory design, carbon nanotube-based designs, organic electronics, FinFET device circuit co-design.

 

Lecture Topics

- Spintronics based Quantum Computing Architecture

- Neuromorphic Computing Using Non-volatile Memory

- Graphene based Interconnect Modelling

- Spintronics-Perspectives and Challenges

- Modeling and Application of FinFET

Gwan-Hyeob Koh is a principal engineer working on memory development at Semiconductor R&D Center, Samsung Electronics. He received B.S., M.S., and Ph.D. degrees in physics from Seoul National University, Seoul, Korea, in 1989, 1991 and 1996 respectively. In 1997, he joined Samsung Electronics and was involved in the development of 1Gb and 4Gb DRAM. From 2002, he has been worked on the development of next generation new memories including MRAM and PRAM. He was involved in the PRAM development from R&D to mass production stage, where his major work was related to process integration, memory device reliability, and yield enhancement. In 2007, he was visiting scholar at EE dept. of Stanford University. His current activity at Samsung Electronics is focused on the development of STT-MRAM. From 2009, he has been serving as a subcommittee member of the international conference on Solid State Devices and Materials (SSDM).

Ioannis (John) Kymissis is an electrical engineer teaching at Columbia University. His area of specialization is solid state electronics and device fabrication, with an emphasis on thin film devices and the use of organic semiconductors in his work. He graduated with his SB, M.Eng., and Ph.D. degrees from MIT, and after working as a post-doc and at QDVison, joined the faculty at Columbia University in 2006. John has won a number of awards for his work, including the NSF CAREER award, the IEEE EDS Paul Rappaport award, the Vodaphone Americas Foundation Wireless Innovation Award, and the MIT Clean Energy Prize. He is currently serving as the editor-in-chief of the Journal of the Society for Information Display and is the general chair for the 2013 Device Research Conference.

 

Lecture Topics

- Organic semiconductors, single chip sensors, flexible electronics, micro-LEDs

 

 

Assaf was born in 1969 in Israel. He received his Ph. D degree from Electrical Engineering department at the Technion, Israel Institute of Technology in 2006. Assaf joined TowerJazz on 2001 and he has been the technology leader in the CMOS-Image-Sensor(CIS) R&D group at TowerJazz Semiconductor from 2002. Assaf was responsible for the image sensor 0.18 technology ramp in 0.18fab in Migdal Haemeq Israel. From 2005 to 2008 he had been developing different device and process schemes for improving pixel dynamic range, noise and sensitivity. This work enabled the transition from CCD technology to CIS in fields like cinema digital photography and Broadcasting. From 2008 Assaf had been working on global shutter pixel technology and Fast Sensors. This work in now widely used in many cameras including Time of Flight (TOF) and structured light 3D, Range Cameras for automotive applications, Industrial and traffic control inspection cameras. Assaf is currently a Senior Principal Engineer at TowerJazz with worldwide responsibly over the CIS technology offering. His current research is focused on low noise GS technology, high resolution NIR imaging and back side illumination devices. Assaf has authored or co-authored more than 30 technical papers in international journals and conference and have 9 issues patents.

Javier Mateos (M’09) was born in Salamanca, Spain, in 1970. He received the B.S. and Ph.D. degrees in physics from the University of Salamanca in 1993 and 1997, respectively. Since 1993, he has been with the Department of Applied Physics of the University of Salamanca, becoming Full Professor in 2017. He was coordinator of EU project ROOTHz aiming at fabricating THz emitters and detectors using semiconductor nanodevices. In addition to THz devices, his present research interests also include the development of novel device concepts using ballistic transport and HEMTs based in both narrow and wide bandgap III–V semiconductors. He is author or co-author of more than 120 indexed journal papers and 200 conference contributions.

Youichi Momiyama received the B.S. and M.S. degree in electronics engineering from Niigata University, Niigata, Japan, in 1990 and 1992, respectively. In 1992, he joined Fujitsu Laboratories Ltd., Atsugi, Japan, where he has been engaged in research and development of low-power and high-speed CMOS devices. He developed the deep sub-micron high-k / metal gate transistor using Ta2O5 / TiN stack in 1997, and accelerated the research and development of high-k materials as a gate stack application. After that, he was engaged in research of RF-CMOS transistor design based on the bulk and SOI technologies for SOC application. He has also been engaged in process integration of 130-45 nm LP and HP technologies at the same time. His present activities include process integration of 32/28 nm node LP and HP technologies, Si MOSFET scaling, device characterization and circuit-device co-design. Mr. Momiyama is a member of the IEEE electron devices society and solid-state circuits society.

Prof. Yong-Young Noh is working as Professor in Department of Chemical Engineering at POSTECH from 2019. He received Ph.D. in 2005 at GIST and then worked at the Cavendish Laboratory as a Post-doc. (2005 – 2007). After then he worked in ETRI as a Senior researcher (2008 – 2009), Hanbat National University as an Assistant professor (2010 – 2012), and Dongguk University-Seoul as an Associate Professor (2013-2018). Prof. Noh has been published more than 270 SCI papers and 60 patents and awarded Merck Young Scientist Award (2013), Korean President Award (2014), IEEE George E. Smith Award (2014), This Month Scientist Award of Korea (2016), and Samsung Display-KIDS Gold Award (2017). He also edited a book entitled “Large Area Flexible Electronics” (John-Wiley VCH). His expertise is in the organic and molecular electronics, printed electronics, and flexible electronics.

Marcelo Antonio Pavanello (S´99-M´02-SM´05) received the Electrical Engineering degree from FEI University in 1993, receiving the award “Instituto de Engenharia” given for the best student among all the modalities of engineering programs offered at FEI. He received the M. Sc. and Ph. D. degrees in 1996 and 2000, respectively, in Electrical Engineering (Microelectronics) from University of São Paulo, Brazil. From August to December 1998 he was with Laboratoire de Microélectronique from Université Catholique de Louvain (UCL), Belgium, working in the fabrication and electrical characterization of novel channel-engineered Silicon-On-Insulator (SOI) transistors. From 2000 to 2002 he was with the Center of Semiconductor Components and Nanotechnologies, State University of Campinas, Brazil, where he worked as a post-doctoral researcher in the development of a CMOS n-well process. Since 2003 he joined FEI University where he is now Full Professor at Electrical Engineering Department. In 2008 he has been with UCL as a visiting professor. Dr. Pavanello is Senior member of The IEEE and Brazilian Microelectronics Society. He is also Research Associate to the National Council for Scientific Development (CNPq), Brazil. Since 2007 he serves as IEEE Electron Devices Society (EDS) Distinguished Lecturer and has been nominated to the Compact Modeling Technical Committee of EDS in 2018. He is author and co-author of more than 300 technical papers in peer-reviewed journals and conferences, and author/editor of 6 books. Dr. Pavanello coordinates several research projects fomented by Brazilian agencies like FAPESP, CNPq and Capes. He also supervised several Ph. D. dissertations, M. Sc. thesis and undergraduate projects in Electrical Engineering. His current interests are the compact modeling, fabrication, electrical characterization and simulation of SOI CMOS transistors with multiple gate configurations and silicon nanowires; the wide temperature range of operation of semiconductor devices; the digital and analog operation of novel channel-engineered SOI devices and circuits.

 

Lecture Topics:

-Junctionless Nanowire Transistors: Electrical Characteristics and Compact Modeling;
-Physics and Electrical Characterization of Multiple-Gate Transistors (Nanowires and FInFETs) in a Wide Temperature Range of Operation;
-Impact of Channel Engineering on SOI Devices and Circuits;
-Operation and Modeling of Silicon-On-Insulator MOSFETs in Cryogenic Environments.

Siddharth Rajan is Associate Professor in the Electrical and Computer Engineering and Material Science and Engineering departments at The Ohio State University, where he joined the faculty in 2008. He received his PhD in Electrical and Computer Engineering in 2006 from University of California, Santa Barbara, and has held research positions in UC Santa Barbara and GE Global Research, NY. His research interests include semiconductor devices and materials, molecular beam epitaxy, transport and heterostructure phenomena, and high frequency transistors. He has co-authored over 100 journal papers.

Huiling Shang received her Ph.D. degree in Electrical Engineering from Lehigh University, Bethlehem, Pennsylvania, in 2001. She joined IBM T. J. Watson Research Center as a research staff member after her graduation. Her research experience includes both strained germanium and silicon-germanium channel CMOS device design and integration, transport physics in ultra thin SOI and FinFET device technologies. In 2006, she took an assignment as Technical Assistant to the Vice-President of IBM SRDC (Semiconductor Research & Development Center). Since then, she has been working in the IBM SRDC on advanced CMOS technology development. From September 2006 to June 2008, she managed the 45nm Bulk CMOS device design group. Starting in July 2008, she has been managing the 22/20nm CMOS device design group. She is a member of the IEEE Electron Device Society AdCom Committee and the VLSI Circuits and Technology Committee.

David Sheridan (SM'17) received his B.S., M.S., and Ph.D. degrees in electrical engineering from Auburn University in 1995, 1997, and 2001, respectively. His research in WBG devices started in 1995 with the development of high temperature SiC devices and packaging and extending to optimization of process, design and edge termination techniques for early multi-kV SiC JBS diodes. From 2001 until 2006 he was with the IBM SRDC working on SiGe technology development. In 2006 he joined SemiSouth Laboratories responsible for product and device design of high voltage (600V-1.7kV) JFETs, JBS didoes, and power modules. In 2012 he joined RFMD to work on high voltage GaN technology development. Since 2015 he has been at Alpha and Omega Semiconductor leading the GaN and SiC power device technology development and products. Dr. Sheridan has authored and co-authored over 80 technical publications, 2 book chapters, awarded more than 30 U.S. patents, and has given several invited talks across a wide range of semiconductor and application topics. He has severed on the committees of several IEEE conferences and standards bodies including IEDM, BCTM, ISPSD, IRPS, ESREF, and the EDS Power Devices and ICs committee.

Gregory Snider was born in Riverside, CA. He received his BSEE degree from the California State Polytechnic University, Pomona in 1983. From 1983 to 1985, he worked for the Motorola Government Electronics Group on integrated circuit design. He received the MSEE and PhD degrees from the University of California, Santa Barbara in 1987 and 1991, where his dissertation research was on the design and fabrication of quantum point contacts. As a post-doc from 1991 to 1993 in the Applied and Engineering Physics Department at Cornell University, he worked on ballistic transport devices. From 1993 to 1994, he worked for Galileo Electro-Optics Corporation on dry-etching techniques for the fabrication of microchannel plates. In 1994 he joined the Department of Electrical Engineering at the University of Notre, serving as Assistant Professor until 2000, as Associate Professor from 2000 to 2005, and as Professor since 2005. His current topics of research concentrate on the area of nanoelectronics and fabrication, molecular electronics, and the issues of the fundamental limits of dissipation in computation. He is a senior member of the IEEE, and a member of the American Physical Society and the American Society of Engineering Education. He has authored or co-authored over 100 journal publications and over 140 conference presentations.

Dr. Venkatasubramanian (Ph.D. Rensselaer, New York, 1988; B.S. Indian Institute of Technology, Madras, India, 1983; Electrical Engineering) is dedicated to the innovation and advancement of several solid state energy conversion materials and device technologies as well as transitioning them to the commercial and defense industries. Dr. Venkatasubramanian is presently at the Johns Hopkins University, Applied Physics Lab as Team Leader for Energy and Thermal Management in the Research and Exploratory Development department. Dr. Venkatasubramanian is also the Co-Founder of Novus Energy Technologies, a spin-off company focused on energy technologies. Until April 2013, Dr. Venkatasubramanian was the Senior Research Director of the Center for Solid State Energetics at RTI International, where he directed innovative basic and applied research in thermoelectrics, photovoltaics, and optoelectronic materials and devices for solid state energy conversion applications. Dr. Venkatasubramanian is the Founder and was also the Chief Technology Officer of Nextreme Thermal Solutions, between 2004-2006, which is commercializing thin-film thermoelectric technology developed under his leadership with DARPA funding; Nextreme was acquired by Laird Technologies in Feb. 2013. Dr. Venkatasubramanian has over 115 peer-reviewed journal and conference publications, 15 issued patents, over 100 presentations in the area of thermoelectric materials and devices, photovoltaics, optoelectronics, and 5 book chapters and edited proceedings. Dr. Venkatasubramanian initiated and developed a research program focused on demonstrating the fundamental advantages of atomically engineered superlattices and other nanoscale materials; this research resulted in the first major breakthrough in the field of thermoelectrics in 40 years (Nature 2001, Nature Nanotechnology 2009), that led to hundreds of laboratories around the world working on other nanoscale thermoelectric materials. Dr. Venkatasubramanian has received two R&D 100 Awards in 2002 and 2010 for thermoelectric innovations, the Margaret Knox Excellence Award for research at RTI in 2002 and Rensselaer’s Allen B. Dumont Prize for research achievements. Dr. Venkatasubramanian was elected Fellow of the IEEE (2011) for contributions to nanoscale thermoelectrics for thermal management of electronics and energy harvesting and a Fellow of AAAS (2012) for seminal contributions to nansocale materials and devices for advanced thermoelectric devices. Dr. Venkatasubramanian has also contributed to advances in multi-junction GaAs-based photovoltaics, received a best paper award at the IEEE First World Conference on PV (1994), and his photovoltaics work has been recognized as key achievements by Department of Energy in 1995-97. Dr. Venkatasubramanian has organized several symposia and has edited proceedings in thermoelectrics, energy harvesting and nanoscale thermal transport for the American Physical Society, Materials Research Society, IEEE and other professional societies.

Runsheng Wang (S’07-M’11) received the B.S. and Ph.D. (highest honors) degrees from Peking University, Beijing, China, in 2005 and 2010, respectively. From November 2008 to August 2009, he was a Visiting Scholar with Purdue University, West Lafayette, IN, USA. He joined Peking University in 2010, where he is currently an Associate Professor at the Institute of Microelectronics. He has authored/coauthored 1 book, 3 book chapters, and over 100 scientific papers, including more than 30 papers published in International Electron Devices Meeting (IEDM) and Symposium on VLSI Technology (VLSI-T). He has been granted 12 US patents and 29 Chinese patents. His current research interests include nanoscale CMOS devices and characterization, circuit and device interaction, and emerging technologies for new-paradigm computing. Dr. Wang was awarded the IEEE EDS Early Career Award by the IEEE Electron Device Society (EDS), NSFC Award for Excellent Young Scientists by the National Natural Science Foundation of China (NSFC), Natural Science Award (First Prize) by the Ministry of Education (MOE) of China, and many other awards. He serves on the Editorial Board of Scientific Reports, and SCIENCE CHINA: Information Sciences, and has served on the Technical Program Committee of many IEEE conferences, including IEDM, IRPS, ICSICT, IPFA, INEC, etc.