Steering Committee

Simon Deleonibus, retired from CEA-LETI on Jan 1st 2016 as Chief Scientist after 30 years of Research on Micro Nanoelectronics Devices Architectures including More Moore More than Moore and Beyond Moore domains emerging devices and architectures: MOSFET scaling technology(bulk, SOI and GeOI), Nanowires FETs ,Tunnel FETs, SET, Non Volatile memories ( Floating gate, RRAM -PCRAM,OxRAM ,CBRAM), Digital,Neuromorphic and Quantum Computing, Sequential/Monolithic and Packaging 3D integration, Interconnect, Field isolation, III-V Power devices, Photovoltaics, MEMS and NEMS, Passive devices, test and modeling/simulation,... and necessary Process steps(lithography - optical and multi ebeams-, etching, thin film deposition and thermal treatments, wafer bonding, physical characterizations,...). 

Before joining CEA-LETI, he was with Thomson Semiconductors(1981-1986), where he developed and transferred to production advanced microelectronics technologies, devices and products (microprocessors, video processors, DSP, DAC and ADC, NVM...). 

He gained his PhD in Applied Physics from Paris University(1982) on Photovoltaics.  He is Visiting Professor at Tokyo Institute of Technology(Tokyo, Japan) since 2014 , National Chiao Tung University(Hsinchu, Taiwan) since 2015 and at Chinese Academy of Science(Beijing, PRC) since 2016 . He is distinguished CEA Research Director(since 2002), IEEE Distinguished Lecturer(since 2004), Fellow of the IEEE (since 2006), Fellow of the Electrochemical Society (since 2015). He was awarded the titles of Chevalier de l’Ordre National du Mérite(2004) and Chevalier de l’Ordre des Palmes Académiques(2011), the 2005 Grand Prix de l’Académie des Technologies. Member of the ITRS since1998, the European Research Council Panel(2007), the Nanosciences Foundation Board of Trustees( 2007). 

He was Associate Editor of IEEE Trans. on Elect. Dev.(2008-2014) and Member of the IEEE Electron Devices Society Board of Governors(01/2009-12/2014) and reelected(2016-2018) ; Chair of IEEE EDS Region 8 SRC (2015-2016) ; Secretary of IEEE Electron Devices Society (2016-2017).

Muhannad S. Bakir received the B.E.E. degree (summa cum laude) from Auburn University, Auburn, AL, in 1999 and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology (Georgia Tech) in 2000 and 2003, respectively. He is currently an Associate Professor and the ON Semiconductor Junior Professor in the School of Electrical and Computer Engineering at Georgia Tech. His areas of interest include three-dimensional (3D) electronic systems, advanced interconnection and packaging, and nanofabrication technology. He is the co-editor (with James D. Meindl) of a book entitled Integrated Interconnect Technologies for 3D Nanoelectronic Systems (Artech House, 2009) and is the author/coauthor of more than 110 journal publications and conference proceedings, 14 US patents, and the presenter of 2 conference tutorials, including an invited tutorial on 3D technology at the 2007 International Solid-State Circuits Conference (ISSCC). Dr. Bakir is the recipient of the 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, 2011 IEEE CPMT Society Outstanding Young Engineer Award, and was an Invited Participant in the 2012 National Academy of Engineering Frontiers of Engineering Symposium. He is also a recipient of the Semiconductor Research Corporation (SRC) Inventor Recognition Awards (2002, 2005, 2009). Dr. Bakir also received twelve conference and student paper awards including one from the IEEE Custom Integrated Circuits Conference (CICC), five from the IEEE Electronic Components and Technology Conference (ECTC), and three from the IEEE International Interconnect Technology Conference (IITC). Dr. Bakir an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology, and was a Guest Editor of the June 2011 Special Issue of IEEE Journal of Selected Topics in Quantum Electronics. He is also a member of the International Technology Roadmap for Semiconductors (ITRS) technical working group for Assembly and Packaging (AP).