T-DMR Editor-in-Chief and Editors

  • T-DMR Editor-in-Chief

    • Anthony S. Oates
      Anthony S.  Oates portrait
      TSMC
      Science Based Industrial Park
      121 Park Ave 3
      Hsinchu 300-77
      Taiwan
      Phone 1:
      866 3 567 3006

      Fax:
      886 3 578 1064
      Anthony S. Oates received the Ph.D. degree in physics from the University
      of Reading, Reading, U.K., in 1985. He was then with the AT&T Bell Laboratories, where his research centered on studies of failure mechanisms in CMOS technologies. During this time, he was appointed as a Distinguished Member of the Technical Staff, and he assumed responsibility for reliability physics development and CMOS technology process qualification. Since 2002, he has been with Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan, where he is responsible for technology reliability
      physics research. He has published over 100 papers in the field of microelectronics reliability, and he is the co-holder of 7 patents. Dr. Oates is a fellow of the IEEE. He is currently the Editor-in-Chief for the IEEE Transactions of Device and Materials Reliability. He served as the General Chair of the International Reliability Physics Symposium in 2001, and was the chair of the IEEE Electron Devices Society Device reliability advisory committee from 2006 to 2011. He has also participated in technical committees for the International Electron Devices Meeting, IPFA, and ESREF symposia. He has edited two conference proceedings on microelectronic materials reliability for the Materials Research Society.

  • T-DMR Editors

    • Gennadi Bersuker
       - Editor
      Gennadi Bersuker portrait
      Sematech
      2706 Montopolis Dr.
      Austin, TX 78741
      USA
      Gennadi Bersuker completed his M.S. and Ph.D. in Physics at the Leningrad State University and Kishinev State University, respectively. After graduation, he joined Moldavian Academy of Sciences, and then worked at Leiden University and the University of Texas at Austin. Since 1994, he has been working at SEMATECH on electrical characterization of Cu/low-k interconnect, high-k gate stacks, advanced memory, and CMOS process development. He has been involved in organizing, chairing, or serving as a committee member in a number of technical conferences, including IRW, IRPS, IEDM, ULSI-TFT, ISAGST, LEC, NGCM, APS. He is a SEMATECH Fellow and has published over 200 papers on the electronic properties of dielectrics and semiconductor processing and reliability.
    • Gianluca Boselli
       - Editor
      Gianluca Boselli  portrait
      Texas Instruments
      13560 North Central Expressway MS 3740
      Dallas, TX 75243
      USA
      Phone 1:
      972 727 7055

      Fax:
      972 995 1724
      Gianluca Boselli completed his Master in EE at the University of Parma, Italy, in 1996. In 2001 he completed his Ph.D. at the University of Twente, The Netherlands, where he worked on high current phenomena in CMOS components.

      In 2001 he joined Texas Instruments, Dallas, Texas, where he focused on ESD and Latch-up development for advanced CMOS technologies, with particular emphasis on process and modeling aspects. In 2007 his responsibilities extended into ESD development of Texas Instruments’ Analog technologies portfolio.

      He authored several papers in the area of ESD and Latch-up. He presented his work at major conferences, including EOS/ESD Symposium, IEDM, and IRPS. He also presented many invited tutorials and papers at various conferences, including EOS/ESD Symposium, IRPS, IEDM, ESREF, IEW and RCJ.

      Dr. Boselli has been the recipient of the “Best Paper Award” on behalf of Microelectronics Reliability Journal in 2000. He received “The Best Paper Award” at the EOS/ESD Symposium 2002. He also received the “Outstanding Symposium Award” at the EOS/ESD Symposium in 2002, 2006 and 2010.

      Dr. Boselli served multiple times as Sub-Committee Chair for Technical Program Committees (TPC) of EOS/ESD Symposium, IRPS, IEW and ESREF. He served as moderator and panelist in many workshops in ESD and Latch-up area.

      Dr. Boselli has served as TPC Chair at the EOS/ESD Symposium 2006, Vice-General Chair at the EOS/ESD Symposium 2007 and General Chair at the EOS/ESD Symposium 2008.

      He is currently a member of the Board of Directors of the ESD Association, where he is the Symposium Business Unit Manager.

      Dr. Boselli is an IEEE senior member and holds fourteen patents with several pending.
    • Yuan Chen
       - Editor
      Yuan Chen portrait
      NASA LaRC
      Electronic Systems Branch
      5 N. Dryden Steet MS 488
      Hampton , VA 23681
      USA
      Phone 1:
      1+ 757 864 3344

      Fax:
      1+ 757 864 7944
      Yuan Chen received her Ph.D. degree in reliability engineering from the University of Maryland at College Park, Maryland, in 1998, with a Graduate Fellowship from the National Institute of Standards and Technologies. From 1999 to 2002, she was a member of technical staff at Bell Labs, Lucent Technologies, and worked on gate oxide reliability, device and circuit reliability, burn-in modeling, and process and technology qualifications. From 2002 to 2009, she was a senior technical member with Electronic Parts Engineering Office, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, California. She is currently a senior member of technical staff with the Electronic Systems Branch, NASA Langley Research Center, Hampton, Virginia, where she is leading the EEE parts engineering efforts at the program level for NASA Constellation Program. Her research area has been focused on product reliability and qualification methodologies, reliability of the extreme environments technologies, and development of reliability characterization and methodologies on microelectronic devices/circuits for space applications. She has authored and co-authored over 40 technical papers. She has been on the management committee and technical review committee for the IEEE International Reliability and Physics Symposium (IRPS) and IEEE International Integrated Reliability Workshop (IIRW), serving as the general chair for IIRW in 2007.
    • Kin P. Cheung
       - Editor
      Kin P. Cheung portrait
      NIST
      100 Bureau Dr MS 8120
      Gaithersburg, MD 20899
      USA
      Dr. Kin P. Cheung, obtained Ph.D. degree in physical chemistry from the New York University in 1983. From 83 to 85 he was a post doc at Bell Laboratories during which he pioneered Terahertz Spectroscopy. From 1985 to 2001 he was a member of technical staff in Bell Laboratories at Murray Hill. From 2001 to 2006, He was an associate professor at Rutgers University. He is currently a project leader at the National Institute of Standards & Technology, Semiconductor Electronics Division. Dr. Cheung published over 140 refereed journal and conference papers. He authored a book on plasma charging damage, a book chapter and edited three conference proceedings. He served in the committee of a number of international conferences and has given tutorial in 10 international conferences. His area of interest is VLSI technology and devices.
    • Felice Crupi
       - Editor
       Felice Crupi  portrait
      University of Calabria
      DEIS Via P. Bucci, 42C
      Arcavacata di Rende
      Cosenza 87036
      Italy
      Phone 1:
      39 0984 494766

      Fax:
      39 0984 494834
      Felice Crupi received the M.S. degree in electronic engineering from the University of Messina, Messina, Italy, in 1997 and the Ph.D. degree from the University of Firenze, Firenze, Italy, in 2001.

      Since 2002, he has been with the Dipartimento di Elettronica, Informatica e Sistemistica, Università della Calabria, Rende, Italy, as an Associate Professor of electronics. Since 1998, he has been a repeat Visiting Scientist with the Interuniversity Micro-Electronics Center (IMEC), Leuven, Belgium. In 2000, he was a Visiting Scientist with the IBM Thomas J. Watson Research Center, Yorktown Heights, NY. His main research interests include reliability of CMOS devices, modeling and simulation of CMOS devices, electrical characterization techniques for solid state electronic devices, the design of ultra‑low noise electronic instrumentation and the design of extremely low power CMOS circuits. He has authored and coauthored more than 80 papers published in peer-reviewed journals and more than 50 papers published in international conference proceedings. He serves or served as a technical program committee member of the IEEE International Electron Devices Meeting (IEDM), and the IEEE International Reliability Physics Symposium (IRPS). He has been the Coordinator of international research projects in the field of semiconductor devices and circuits.
    • Weileun Fang
       - Editor
      Weileun  Fang portrait
      National Tsing Hua University
      Power Mechanical Eng
      NEMS Inst
      Hsinchu 300
      Taiwan
      Phone 1:
      1 886 3 574 2923

      Fax:
      886 3 572 2840
      Prof. Fang was born in Taipei, Taiwan. He has been working in the MEMS field for 20 years. He received his Ph.D. degree from Carnegie Mellon University (Pittsburgh, PA) in 1995. His doctoral research focused on the determining of the mechanical properties of thin films using MEMS structures. In 1995, he worked as a postdoctoral research for LIGA project at Synchrotron Radiation Research Center, Taiwan. He joined the Power Mechanical Engineering Department at the National Tsing Hua University (Taiwan) in 1996, where he is now a Professor as well as a faculty of NEMS Institute. From June to September 1999, he was at California Inst. of Tech. as a visiting associate. He has established a world-class MEMS testing and characterization lab. His research interests include MEMS with emphasis on micro physical sensors and actuators, micro fabrication/packaging technologies, CMOS MEMS, micro optical systems, and characterization of thin film mechanical properties.

      Prof. Fang has published more than 110 SCI journal papers, near 180 international conference papers, and 60 patents (all in MEMS field). He is now the Board Member of JMM (SCI journal), and the Associate Editor of IEEE Sensors J., JM3 (SCI journals) and JSTS (J. of Semiconductor Tech. and Science, published by the IEE of Korea). He has served as the chief delegate of Taiwan for World Micromachine Summit since 2008. He also served as the TPC (Technical program committee) of IEEE MEMS’04, MEMS’07, and MEMS’10, the TPC of Transducers’07, and the EPC of Transducers’09 and Transducers’11. He has become the member of international steering committee of Transducers from 2009. He serves as the Asia Regional Program Co-Chair of IEEE Sensors 2010, and the TPC Chair of IEEE NEMS 2011. He also serves as the Steering Committee for APCOT (Asia Pacific Conf. on Transducers) from 2008-2012, and the TPC Co-chair for APCOT 2008.

      There are 26 PhD and 60 Master students graduated from Prof. Fang’s group so far. Most of them are working in the MEMS and micro sensors related companies, such as TSMC, UMC, ADI, InvenSense, Qualcomm, APM, tMt, Sitronix, PixArt, Domintech, WindTop, etc. He is now the MEMS committee member of SEMI Taiwan. He is the standing committee member of the Nanotechnology and Micro System Association (NMA), Taiwan. He also serves as the chair of the Technology Development and the International Collaboration Committee in NMA. Moreover, Prof. Fang serves as the technical consultant for many MEMS companies in Taiwan.

    • Jacopo Franco, PhD
       - Senior Researcher
      Jacopo Franco, PhD portrait
      Jacopo Franco received the B.Sc. (2005) and M.Sc. (2008) in Electronic Engineering cum laude from the University of Calabria, Italy, and the Ph.D. in Engineering summa cum laude with the Congratulations of the Board of Examiners from KU Leuven, Belgium (2013), defending a Dissertation entitled “Reliability of High Mobility (Si)Ge Channel pMOSFETs for Future CMOS Application—Toward Reliable Ultra-Thin EOT Nanoscale Transistors”. As of Feb. 2013, he holds a permanent position as Senior Researcher in the Device Reliability and Advanced Electrical Characterization (DRE) group of imec, Leuven - Belgium. His main research interests focus on the reliability of Si, SiGe, Ge and III-V channel transistors for future CMOS nodes, and on time-dependent variability issues in nanoscale logic devices. He has (co-)authored 170+ publications in international journals and conference proceedings, including 20+ invited papers, 1 book, 3 book chapters, 20 IEEE International Electron Device Meeting (IEDM) papers, 17 VLSI Technology Symposium papers, 30+ IEEE International Reliability Physics Symposium (IRPS) papers, 2 international patents. He has served as a member of the Management Committee of the IEEE International Integrated Reliability Workshop (IIRW) and he is currently serving as a member of the Technical Program Committees of IRPS (subcommittees: Transistors 2014,2016; Process Integration 2015) and IIRW (2014-2016). In 2009 he received the IEEE Nicollian Award for the Best Student Presentation at the IEEE Semiconductor Interface Specialists Conference (SISC). Later on, he received the IEEE Electron Device Society (EDS) Ph.D. Student Fellowship 2012 “for the demonstration of significant ability to perform individual research and a proven record of academic excellence”. In 2016 he has been selected as one of the three runner-ups for the Elsevier Microelectronic Engineering Young Investigator award. He is also one of the recipients of the IEEE Paul Rappaport Award 2011 “for the best paper of the year in the journals of the Electron Device Society”, and of the Best Paper (2012), Outstanding Paper (2014), and Best Student Paper (2016) awards at IRPS.

    • Martin Gall
       - Editor
      Martin Gall portrait
      Frauhofer Institute for Nondestructive Testing IZFP
      Materials and Reliability for Micro-and Nanoelectronics
      Dresden Branch Maria-Reiche-Str 2
      Dresden D-01109
      Germany
      Phone 1:
      49 351 88815 524

      Fax:
      49 351 88815 509


      Dr. Martin Gall is currently department head of Materials and Reliability for Micro- and Nanoelectronics at the Fraunhofer Institute for Nondestructive Testing in Dresden, Germany (FhG IZFP-D). He received the title of Diplomphysiker (M.S. in physics) from the Rheinisch-Westfaelische Technische Hochschule Aachen, Germany, in 1992, and a Ph.D. in materials science and engineering from The University of Texas at Austin, USA, in 1999. He joined the Motorola Semiconductor Division (later to become Freescale Semiconductor) in 1995 as an engineer and has since been working in the area of backend reliability, mainly addressing issues with electromigration, stress-induced voiding, and time-dependent dielectric breakdown. From 2002 until 2009, he managed the interconnect reliability team in Freescale Semiconductor’s Technology Solutions Organization, mainly focusing on implementation of advanced, low-k dielectrics in the 65, 45, 32 and 22 nm nodes. From 2007 until 2009, he was assigned to the IBM/Freescale Semiconductor Technology Alliance in Yorktown Heights and Hopewell Junction, NY. He relocated back to Europe in 2010 to join GLOBALFOUNDRIES, Dresden, Germany, and subsequently the Fraunhofer Institute in 2011.
    • Chao-Kun Hu
       - Editor
      Chao-Kun Hu portrait
      IBM
      IBM T. J. Watson Research Ctr
      Si Technology
      Yorktown Heights, NY 10598
      USA
      Phone 1:
      1 914 945 2378

      Fax:
      1 914 945 2141


      Dr. Chao-Kun Hu is a Research Staff Member in the Reliability and Materials Sciences Department at the Thomas J. Watson Research Center of IBM. He received his Ph.D. degree in physics from Brandeis University in 1979. He was a research associate at Rensselaer Polytechnic Institute before he joined IBM in 1984. He was involved in the development of multilevel on-chip Cu and Al(Cu) interconnections fabrications at the IBM Yorktown Silicon Facility. His current research is in the area of on-chip interconnections electromigration reliability. He received IBM Research Division Award for the first demonstration of integration of Cu-polyimide wiring on silicon IC chips in 1991. He was one of the recipients of IBM Outstanding Technical Achievement Award in 1998, IBM Corporate Awards in 1999 and 2006 in appreciation for his contributions in Copper Interconnect Technology and Invention of The Year 2006 by NY Intellectual Property Law Association.
    • Agis A. Iliadis
       - Editor
      Agis A.  Iliadis portrait
      University of Maryland
      Electrical and Computer Eng
      Paint Branch Drive
      College Park, MD 20742
      USA
      Phone 1:
      +1 301 405 3651

      Fax:
      +1 301 314 9281

      Agis A. Iliadis (M’83–SM’01) received his MS and PhD degrees in Electrical and Electronic Engineering from the Department of Electrical Engineering and Electronics, University of Manchester Institute of Science and Technology (UMIST), Manchester, U.K. He is a Professor in the Department of Electrical and Computer Engineering, the Director of the Semiconductor Nanotechnology Research Laboratory, and a member of the Maryland NanoCenter, of the University of Maryland, College Park, Maryland, USA. He is a member of the IEEE Electron Device Society and IEEE Reliability Society, a Distinguished Lecturer of the IEEE Electron Device Society, an Ad-Com member of the IEEE EDS Educational Activities Committee, and the Chair of the IEEE-EDS Master and PhD Student Fellowship Committee. He has served as an Ad-Com member of the IEEE-EDS Technical Committee on Electronic Materials, and was the EDS Representative of the IEEE-USA Professional Activities Board (PACE). He is also a member of the Society of Photonic and Instrumentation Engineers (SPIE), and the Institute of Physics (U.K.). He has organized and served in several Conference Committees. His contributions and research interests focus on improving performance and reliability of electronic devices and materials, including ohmic and Schottky metallizations in III-V and wide band gap semiconductors, the development of metal-oxide semiconductor nanostructures like ZnO through self-assembly and thin films through pulsed laser deposition on Si and other substrates, nanostructured chemical sensors, surface acoustic wave (SAW) bio sensors, and the effects of electromagnetic interference on CMOS ICs.
    • Ming-Dou Ker
       - Editor
      Ming-Dou Ker portrait
      National Chiao Tung University, Taiwan
      Electronics Engineering
      1001 University Road
      Hsinchu 300
      Taiwan
      Phone 1:
      +886-3-5131573

      Fax:
      +886-3-5715412

      Lecture Topics:


      [1] On-Chip ESD Protection Design in Nano CMOS.


      [2] ESD Protection Design for RF and Giga-Hz I/O Circuits.


      [3] System-Level ESD Protection: chip-level and board-level solutions.


      [4] Transient-Induced Latchup in CMOS ICs. [5] ESD Protection in HV CMOS.

    • Pey Kin Leong
       - Editor
      Pey Kin Leong  portrait
      Nanyang Technological University
      School of Electrical and Electronic Eng.
      287 Ghim Moh Road #04-00
      Singapore 279623
      Singapore
      Phone 1:
      +65 67906371

      Fax:
      +65 68989624
      Dr. Pey Kin Leong received his Bachelor of Engineering (1989) and Ph.D (1994) in Electrical Engineering from the National University of Singapore. He has held various research positions in the Institute of Microelectronics, Chartered Semiconductor Manufacturing, Agilent Technologies and National University of Singapore. He is currently a Professor, Head of the Microelectronics Division, Director of Nanyang Nanofabrication Center and Director of the Microelectronic Center in the School of Electrical & Electronics Engineering, Nanyang Technological University, Singapore and holds a concurrent Fellowship appointment in the Singapore-MIT Alliance (SMA).

      Dr. Pey is a senior member of IEEE and an IEEE EDS Distinguished Lecturer, and has been the organizing committee member of IPFA since 1995. He was the General Chair of IPFA2001, Singapore and the co-General Chair of IPFA2004, Hsinchu, Taiwan. KL Pey was the Guest Editor of IEEE Transactions on Devices and Materials Reliability in 2003-05, and the Chair of the Singapore IEEE REL/CPMT/ED Chapter in 2004/05 and 2009 and served on the 2006/07/08 IRPS technical subcommittee, IPFA’02 to IPFA’06, IPFA’08 and IPFA’09 technical subcommittee and 2007 IEDM CMOS & Interconnect Reliability and 2008 IEDM Characterization, Reliability and Yield sub-committee.

      Dr. Pey has published more than 145 international refereed publications and 150 technical papers at international meetings/conferences and holds 33 US patents. Dr. Pey's research focuses are on pulsed laser annealing for channel engineering for nano-scale CMOS, advanced alloy silicide for nanostructures and nanodevices and transistor reliability in dielectric breakdown and advanced interconnects. Dr. Pey pioneers in using physical analysis techniques such as TEM and EELS in the study of breakdown mechanisms in ultrathin SiON and high-k gate stack.
    • Chee Wee Liu
       - Editor
      Chee Wee Liu portrait
      National Taiwan University
      Electrical Engineering
      No 1 Sec 4 Roosevelt
      Taipei 106
      Taiwan
      Phone 1:
      866 2 336 63700

      Fax:
      866 2 236 40078
      Chee Wee Liu (M’99–SM’00) received the B.S. and M.S. degrees in electrical engineering from the National Taiwan University (NTU), Taipei, Taiwan, in 1985 and 1987, respectively, and the Ph.D. degree in electrical engineering from Princeton University, Princeton, NJ, in 1994.

      /Vs at low temperature. He was the IEDM TPC member in 2008-2009 and subcommittee chair (SSN) in 2010. He received 2003-2005 Outstanding Research Award, National Science Council, Taiwan. Details in http://nanosioe.ee.ntu.edu.tw
    • Shankar N. Ekkanath Madathil
       - Solid State Power Devices
      Shankar N. Ekkanath  Madathil portrait
      University of Sheffield
      Rolls Royce and Royal Academy of Engineering, Electronics and Electric Engineering
      Mappin Street
      Sheffield S1 3JD
      UK
      Phone 1:
      44 114 222 5856

      Ekkanath Madathil Sankara Narayanan (M’87–SM’00) was born in India, in 1962. He received his B.Sc. and M.Sc. degrees from PSG College of Technology, Coimbatore, India, M.Tech degree from the Indian Institute of Science, Bangalore and his Ph.D. degree from the University of Cambridge, U.K. He was a Maudslay Engineering Research Fellow in Pembroke College, Cambridge and a Research Associate with Engineering Department, Cambridge University during 1992–1994. He was the Director of the Emerging Technologies Research Center, De Montfort University, UK during 1994–2007. He is currently with the Electrical Machines and Drives Research Group at the University of Sheffield in the UK, where he holds the Rolls Royce/Royal Academy of Engineering Chair in Power Electronics Systems and Royal Society Industry Fellowship in Rolls-Royce, UK. His research interests include integrated and discrete power device technologies in Silicon and wide band gap materials, design for manufacturability and compact power converters for automotive/aerospace applications, functional materials, thin film transistors, RF technologies, and technology strategies in microelectronics. He is an author of more than 200 articles and holds twenty five patents, approved or pending approval. He is a Fellow of IET and IOP. He is in the editorial boards of IEEE Transactions on Devices and Materials Reliability and IET Journal of Power Electronics.

    • Balu Pathangey
       - Editor
      Balu Pathangey portrait
      Intel
      ATD Q&R
      5000 W Chandler Blvd CH5-263
      Chandler, AZ 85226
      USA
      Phone 1:
      1 408 552 5838

      Balu Pathangey received his Ph.D degree in Chemical Engineering from Stevens Institute of Technology, Hoboken, NJ, in 1988. He spent 10 years with University of Florida, Gainesville, Fl, on the compound semiconductor thin film growth and characterization projects for optoelectronic applications, 2 years at a semiconductor equipment startup company in Tempe, AZ, on the development of atomic layer deposition systems for copper metallization and high-k oxide materials, 4 years at Intel’s first high volume manufacturing of copper based CPUs in the quality and reliability group, and is currently a senior member of engineering staff at Intel’s quality and reliability labs in Chandler, AZ, focusing on assembly technology development related to material interface issues. He has published over 30 papers on chemical engineering and materials technology topics including invited publications in IEEE-TDMR and been granted 2 patents. He also serves in the advisory board of a charitable trust for providing AIDS related test and treatment facility in Mysore, India.

    • C. Glenn Shirley
       - Editor
      C. Glenn  Shirley portrait
      Portland State University Maseeh
      College of Engineering and Computer Science
      ECE
      Portland, OR 97207-0751
      USA
      Phone 1:
      1 503 799 6452

      Dr. C. Glenn Shirley is an adjunct faculty member with the Integrated Circuit Design and Test Laboratory in the ECE department at Portland State University (Oregon). He retired in 2007 after 23 years at Intel, anda prior 10 years at Motorola, U.S. Steel and Carnegie-Mellon University (post-doc). At Intel Dr. Shirley worked and published on package reliability, moisture reliability of silicon, accelerated moisture test hardware (HAST), and industry standards. He also led the development of Intel’s burn-in methodology, founded a manufacturing test technology development Q&R group, and started a Q&R statistical modeling group. Subsequently he co-directed, as Intel’s Q&R Systems Architect, a department reponsible for Intel’s quality systems. Dr. Shirley’s current interests include yield/quality/reliabilitystatistical modeling of manufacturing test. Dr. Shirley holds a PhD in Physics from Arizona State University, and an MSc in Physics from the University of Melbourne (Australia).
    • Cher Ming Tan
       - Editor
      Cher Ming Tan portrait
      Chang Gung University
      259 Wen Hua 1st Road
      TaoyuanTaiwan
      Phone 1:
      +886-32118800 Ext 5952

      Dr. Tan received his Ph.D in Electrical Engineering from the University of Toronto in 1992. He has 10 years of working experiences in reliability in electronic industry (both Singapore and Taiwan) before joining Nanyang Technological University (NTU) as faculty member in 1996 till 2014. He joined Chang Gung University, Taiwan and set up a research Center on Reliability Sciences and Technologies in Taiwan and acts as Center Director. He is Professor in Electronic Department of Chang Gung University, Honorary Chair Professor in Ming Chi University of Technology, Taiwan. He has published 300+ International Journal and Conference papers, and giving 10+ keynote talks and 50+ invited talks in International Conferences and several tutorials in International Conferences. He holds 12 patents and 1 copyright on reliability software. He has written 4 books and 3 book chapters in the field of reliability. He is an Editor of Scientific Report, Nature Publishing Group, an Editor of IEEE TDMR and Series Editor of SpringerBrief in Reliability. He is a member of the advisory panel of Elsevier Publishing Group. He is also in the Technical committee of IEEE IRPS.
      He is a past chair of IEEE Singapore Section, senior member of IEEE and ASQ, Distinguish Lecturer of IEEE Electronic Device Society on reliability, Founding Chair and current Chair of IEEE Nanotechnology Chapter - Singapore Section, Fellow of Institute of Engineers, Singapore, and Fellow of Singapore Quality Institute. He is the Founding Chair of IEEE International Conference on Nanoelectronics, General Chair of ANQ Congress 2014. He is also the recipient of IEEE Region 10 Outstanding Volunteer Award in 2011. He is Guest Editor of International J. of Nanotechnology, Nano-research letter and Microelectronic Reliability. He is in the reviewer board of several International Journals such as Thin Solid Film, Microelectronic Reliability, various IEEE Transactions, Reliability Engineering and System Safety etc for more than 5 years. He is the only individual recipient of Ishikawa-Kano Quality Award in Singapore since 2014. He is also current active in providing consultation to multi-national corporations on reliability.
      His research interests include reliability and failure physics modeling of electronic components and systems, finite element modeling of materials degradation, statistical modeling of engineering systems, nano-materials and devices reliability, and prognosis & health management of engineering system.

      For more detail, please visit www.chermingtan.com
    • Massimo Vanzi
       - Editor
      Massimo Vanzi portrait
      University Cagliari
      Electrical and Electronics Engineering DIEE
      Piazza D' Armi
      Calgliari 09123
      Italy
      Phone 1:
      39 070 675 5775

      Fax:
      39 070 675 5900

      Massimo Vanzi (Bologna, May 13, 1954) graduated in Physics at the University of Bologna in 1978.

      From 1980 to 1992 he worked at Telettra S.p.A. on studying reliability issue of semiconductor electronic circuits and analytical techniques development required from these activities.

      In the 1985/1986 he was Senior Expert of the ONU's ITU Agency at Telebras, Campinas, Brazil.

      On 1992 he became Associated Professor of Solid State Electronics at the Electronic Engineering Course of the University of Cagliari.

      Since then, he focused his work on Reliability, by means of much cooperation with European Labs, like ETH Zurich, IXL Bordeaux, Fraunhofer inst. Darmstadt. Particular efforts have been spent on photonic devices, within cooperation with Pirelli Cavi, Milan.

      Since 1998 he opened the course of Reliability and Diagnostics of Electron Devices and Systems, where he gives account of the know-how and of the daily upgrading on technology, characterization and analysis on electron and photon devices.

      Since October 2001 he is Full Professor of Electronics.

      On 2001 he was the General Chairman of the International Workshop on Compound Semiconductor Devices and Integrated Circuits (WOCSDICE2001, May, Cagliari) and for the year 2002 he is the Chairman of the Technical Committee of ESREF 2002, one of the three international appointments (the only European one) on Reliability and Diagnostics of semiconductor Devices.

      On 2007/08 he has been a member of the ESA Work Group on Laser Diodes, whose task is the definition of the qualification criteria for such devices in space applications.

      On 2009 and 2010 he has been the organizer and the scientific chairman of the 1st and 2nd International Symposium on Reliability of Optoelectronics for Space applications (ISROS2009), a new event focused on reliability of photonic devices in such a special environment as space. The worldwide adhesion of all the space agencies has welcome this proposal, together with the participation of the most important experts in the field of reliability of photonics.



      The M. Vanzi's research topics are the physical and electrical characterization of semiconductor electronic devices and the physics mechanism of failures discovered.

      This activity is divided into the following chief arguments:



      - Characterization of technologies and electronic devices Micrologics TTL-Schottky: study of metal boundaries degradation into the CMOS Schottky bipolar devices.

      The study of the Latch-Up phenomena into the CMOS devices using electron microscopy special techniques. VLSI devices.

      Microelectronic modelling and planning of a test pattern for studying current crowding phenomena of metal-semiconductor contacts.

      Particle detectors. Theoretical interpretation of signals propagation into microstrip detectors.

      - Development and application of new investigation techniques, especially for large scale integration devices and photonic devices.

      TEM: study of tunneling phenomena onto rough surface with 3D maps obtained from TEM images statistics. TEM analysis of semiconductor laser degradations.

      Electronic holography: theoretical and practical study of Schroedinger wave distortions made from microfields associated to pn junctions observed by TEM.

      EBIC/FIB/TEM: procedure for analyzing by TEM the degradations of semiconductor laser.

      EBT: development and design patent of a new technique for isolating the logical anomalies of integrated devices comparing Voltage Contrast maps.

      - Reliability of new developed technologies (programmable devices, ECL devices, Schottky, COMS, plastic package devices, MESFETs, Laser)

      The researches on compound semiconductor devices (GaN MESFETs) and on optoelectronic devices (TLC Lasers) are relevant in this project.

      GaAs MESFETs and GaAs HEMTs: study of thermic effects made from high currents and high temperatures associated with these:

      the parametric degradations of MESFETs have been explained from the identification of electromigration effects into more stressed metallization and of gate metallization/semiconductor penetration (gate sinking).

      Development of an innovative technique to detect the "gate sinking" phenomena through selective removal criteria of semiconductor layer for observing back metal contact surface.

      TEM employment for observing thin sections of real devices for studying and characterizing no alloy ohmic contacts on GaN. Some variations driven from continued thermic treatments of GaAs/Pd/Ge contacts have been detected using this technique; other techniques did not found explanation for the resistance increasing.

      Microinteractions visualization of contacts of gate submicrometric Schottky Ti/Pt/Au - GaAs devices carrying out life tests and correspondence of these phenomena with electrical observed characteristics.