Compact Modeling Committee

  • Compact Modeling Committee Chair

    • Benjamin Iniguez
       - Device and Process Modelling
      Senior Member
      Universitat Rovira i Virgili (URV)
      Avinguda dels Paisos Catalans 26
      Tarragona 43007
      Spain
      Phone 1:
      34 977558521

      Fax:
      34 977559605
      Benjamin Iñiguez obtained the Ph D in Physics in 1992 and 1996, respectively, from the Universitat de les Illes Balears (UIB). From February 1997 to September 1998 he was working as a Postdoctoral Researcher at the Rensselaer Polytecnhnic Institute in Troy (NY, USA). From September 1998 to January 2001 he was working as a Postdoctoral Scientist in the Université catholique de Louvain (Louvain-la-Neuve, Belgium), supported by two Marie Curie Fellowships from the European Commission. In February 2001 he joined the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA)of the Universitat Rovira i Virgili (URV), in Tarragona, Catalonia, Spain) as Titular Professor. In February 2010 he became Full Professor at URV. He obtained the Distinction from the Generalitat for the Promotion of University Research in 2004 and the ICREA Academia Award (the highest award for university professors in Catalonia, from ICREA Institute) in 2009 and 2014, for a period of 5 years each. He led one EU-funded project (“COMON”, 2008-12) devoted to the compact modeling of nanoscale semiconductor devices and he is currently leading one new EU-funded project (DOMINO, 2014-18) targeting the compact modeling of organic and oxide TFTs.
      His main research interests are the characterization, parameter extraction and compact modelling of emerging semiconductor devices, in particularorganic and oxide Thin-Film Transistors, nanoscale Multi-Gate MOSFETs and GaN HEMTs. He has published more than 150 research papers in international journals and more than 130 abstracts in proceedings of conferences.
  • Compact Modeling Committee Members

    • Yogesh Singh Chauhan
       - Device and Process Modeling
      Indian Institute of Technology (IIT) Kanpur
      Department of Electrical Engineering
      Kanpur, U.P. 208016
      India
      Phone 1:
      +91-512-6797244

      Phone 2
      +91-512-6797257

      Phone 3:
      +91-8853669988 (mobile)

      Yogesh Singh Chauhan (SM'12) is an associate professor at IIT Kanpur, India. He was with Semiconductor Research & Development Center at IBM in 2007 – 2010, Tokyo Institute of Technology in 2010 and University of California Berkeley in 2010-2012. He is the lead developer of industry standard BSIM-BULK (formerly BSIM6) model. He is the co-developer of ASM-HEMT model for GaN HEMTs, which is under industry standardization at the Compact Model Coalition (CMC). He was technical program committee member of IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2013 and IEEE European Solid-State Device Research Conference (ESSDERC) 2016/2017. He is the member of IEEE-EDS Compact Modeling Committee. He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015. His research interests are characterization, modeling, and simulation of semiconductor devices.
    • Jung-Suk Goo
    • Wladyslaw Grabinski
      MOS-AK Association
      CH-1291Commugny
      Station 11
      Lausanne CH-1015
      Switzerland
      Phone 1:
      +41 79 883 6076

      Lecture Topics:
      Electrical Characterization (DC, CV, RF)
      TCAD Process/Device Simulations
      SPICE/Compact Modeling
      Verilog-A Standardization
    • Marek Mierzwinski
    • Slobodan Mijalkovic
    • Marcelo Pavanello
       - Senior Member
      Centro Universitario FEI
      Av. Humberto de Alencar Castelo Branco, 3972
      Sao Bernardo do Campo, Sao Paulo 09850-901
      Brazil
      Phone 1:
      +551143532913

      Lecture Topics: Topics for Distinguished Lecturer Talks:
      1. "Junctionless Nanowire Transistors: Perspectives for the Nanometer Era";
      2. "Junctionless Nanowire Transistors: Static and Dynamic Modeling";
      3. “Performance and Low Frequency Noise of Nanowires”
      4. "Physics and Electrical Characterization of Multiple Gate Transistors";
      5. "Device and Circuit Improvements of Asymmetric Channel Transistors".

      Marcelo Antonio Pavanello (S´99-M´02-SM´05) received the Electrical Engineering degree from FEI University in 1993, receiving the award “Instituto de Engenharia” given for the best student among all the modalities of engineering programs offered at FEI. He received the M. Sc. and Ph. D. degrees in 1996 and 2000, respectively, in Electrical Engineering (Microelectronics) from University of São Paulo, Brazil. From August to December 1998 he was with Laboratoire de Microélectronique from Université Catholique de Louvain (UCL), Belgium, working in the fabrication and electrical characterization of novel channel-engineered Silicon-On-Insulator (SOI) transistors. From 2000 to 2002 he was with the Center of Semiconductor Components and Nanotechnologies, State University of Campinas, Brazil, where he worked as a post-doctoral researcher in the development of a CMOS n-well process. Since 2003 he joined FEI University where he is now Full Professor at Electrical Engineering Department. In 2008 he has been with UCL as a visiting professor.

      Dr. Pavanello is Senior member of The IEEE and Brazilian Microelectronics Society. He is also Research Associate to the National Council for Scientific Development (CNPq), Brazil. Since 2007 he serves as IEEE Electron Devices Society (EDS) Distinguished Lecturer and has been nominated to the Compact Modeling Technical Committee of EDS in 2018.

      He is author and co-author of more than 300 technical papers in peer-reviewed journals and conferences, and author/editor of 6 books. Dr. Pavanello coordinates several research projects fomented by Brazilian agencies like FAPESP, CNPq and Capes. He also supervised several Ph. D. dissertations, M. Sc. thesis and undergraduate projects in Electrical Engineering.

      His current interests are the compact modeling, fabrication, electrical characterization and simulation of SOI CMOS transistors with multiple gate configurations and silicon nanowires; the wide temperature range of operation of semiconductor devices; the digital and analog operation of novel channel-engineered SOI devices and circuits.
    • Kejun Xia
      Kaikai Xu received the B.S. degree from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, and the Ph.D. degree from the University of California at Irvine (UCI), USA, in collaboration with the California Institute for Telecommunications and Information Technology. Currently, he is an Associate Professor with the University of Electronic Science and Technology of China, Chengdu, China, and is a Distinguished Professor (1000-Talents Program) of Sichuan Province, China. He is also on the Technical Advisory Board for the International System-on-Chip (SoC) Conference, Exhibit & Workshops (SOC Irvine) and serves on the editorial board for Microelectronics Journal.
      His research interest includes semiconductor devices and analog CMOS IC design, especial on the subject of characterization, parameter extraction and compact modeling of emerging semiconductor devices.