Device Reliability Physics Committee

  • Device Reliability Physics Committee Chair

    • Souvik Mahapatra
       - Fellow Member
      IIT Bombay
      Dept. of Electrical Engineering
      Maharashtra , Powai, Mumbai 400076
      Phone 1:
      +91 22 2572 0408

      Souvik Mahapatra received his PhD from IIT Bombay in 1999. During 2000-01, he was with Bell Laboratories, Murray Hill, NJ, USA. Since 2002, he is with the Department of Electrical Engineering at IIT Bombay and presently a full professor. His current research interests are CMOS device scaling and reliability, and device-circuit co-design for co-optimisation of power, performance and reliability. He has published more that 150 papers in peer reviewed journals and international conferences, delivered invited talks at major international conferences including IEEE IEDM and IRPS, and has been actively collaborating with several global semiconductor industries. He is a fellow of IEEE (for contributions to CMOS transistor gate stack reliability), fellow of Indian National Academy of Engineering, fellow of Indian Academy of Sciences, and a distinguished lecturer of IEEE Electron Devices Society.
  • Device Reliability Physics Committee Members

    • Bharat Bhuva
      Vanderbilt University
    • Jifa Hao
      Fairchild Semiconductor
      Portland, MN
    • Andreas Kerber
      Global Foundries
      2070 Route 52
      Hopewell Junction 12533
      Phone 1:

      Andreas Kerber was born in Schnann, Austria. He received his Diploma in physics from the University of Innsbruck, Austria, in 2001 and a PhD in electrical engineering from the TU-Darmstadt, Germany in 2004 (granted with honors). He worked as an intern at Bell Laboratories, Lucent Technologies, Murray Hill, NJ, USA (1999-2000), at IMEC in Leuven, Belgium (2001-03) as Infineon Technologies assignee to International SEMATECH, for the Reliability Methodology Department at Infineon Technologies in Munich, Germany (2004-06), for AMD in Yorktown Heights, NY (2006-09), and as a Prinicpal Member of Technical Staff for GLOBALFOUNDRIES in Malta, NY (since 2009). Much of his work centered around Front-End-Of-Line (FEOL) reliability research with focus on metal gate / high-k CMOS technologies. He has co-authored over 100 papers in Journals and Conferences, is an IEEE senior member (since 2011) and an IEEE Distinguished Lecturer for the Electron Device Society (since 2016).
    • Durga Misra
       - Senior Member
      NJ Institute of Technology
      Electrical and Comp. Eng. Department
      323 M L King Blvd.
      Newark, NJ 07102-1824
      Phone 1:
      +1 973 596 5739

      Lecture Topics:
      1. Challenges for Nanoelectronics: More Moore and More than Moore.
      2. High-k on High-Mobility Substrates: An interface Issue
    • Chandra Mouli
       - Memory Devices and Technology; Solid State Device Phenomena
      Micron technology Inc.
      8000 S. Federal Way R&D MS 1-720
      Boise, ID 83706
      Phone 1:
      +1 208 368 2092

      +1 208 368 2548
      Chandra Mouli is with Micron Technology Inc., Boise, ID, USA. He is currently Director of Device Technology with responsibilities in the area of advanced device characterization, reliability analysis, test structure design/layout, process & device modeling for all technologies under development in R&D.

      He received his undergraduate degree in Physics and MSEE from the Indian Institute of Science (IISc), Bangalore, India and Ph.D (EE) from the University of Texas at Austin. He was with Texas Instruments for couple of years before joining UT/Austin. His interests include semiconductor devices and process technology for advanced memory, opto-electronic devices, exploratory research in the area of new materials and device structures. He has more than hundred issued patents and several pending in various areas of semiconductor devices and process – in advanced memory, novel devices and image sensor technology. He has served in the technical committees for various conferences, including IEDM, IRPS and SISPAD. He has also served in the review committees for NSF and SRC. He is currently a member of the scientific advisory board in SRC’s focus center programs and is a member of the ITRS technical working group.
    • Anthony S. Oates
      Science Based Industrial Park
      121 Park Ave 3
      Hsinchu 300-77
      Phone 1:
      866 3 567 3006

      886 3 578 1064
      Anthony S. Oates received the Ph.D. degree in physics from the University
      of Reading, Reading, U.K., in 1985. He was then with the AT&T Bell Laboratories, where his research centered on studies of failure mechanisms in CMOS technologies. During this time, he was appointed as a Distinguished Member of the Technical Staff, and he assumed responsibility for reliability physics development and CMOS technology process qualification. Since 2002, he has been with Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan, where he is responsible for technology reliability
      physics research. He has published over 100 papers in the field of microelectronics reliability, and he is the co-holder of 7 patents. Dr. Oates is a fellow of the IEEE. He is currently the Editor-in-Chief for the IEEE Transactions of Device and Materials Reliability. He served as the General Chair of the International Reliability Physics Symposium in 2001, and was the chair of the IEEE Electron Devices Society Device reliability advisory committee from 2006 to 2011. He has also participated in technical committees for the International Electron Devices Meeting, IPFA, and ESREF symposia. He has edited two conference proceedings on microelectronic materials reliability for the Materials Research Society.
    • Stephen Ramey
    • Mayank Shrivastava
       - Assistant Professor
      Indian Institute of Science Bangalore
      Department of Electronic Systems Engineering
      Bangalore 560012
      Dr. Mayank Shrivastava received his PhD degree from Indian Institute of Technology Bombay. He has over 90 international publications and 40+ patents. His one of the key contributions has been development, enablement and integration of nanoscale CMOS and power MOSFET devices in advanced CMOS nodes for System on Chip (SoC) applications. He is among the first recipient of Indian section of American TR35 award (2010). He is also the first Indian to receive IEEE EDS Early Career Award (2015). In addition to this he is an IEEE Senior Member and has received several other awards and honors including 2008 best research paper award from Intel Corporation Asia academic forum; excellence in research award for his PhD thesis in 2010 and industrial impact award from IIT Bombay in 2008. Dr. Shrivastava’s current research deals with experimentation, design and modelling of beyond CMOS devices using Graphene and TMDCs, wide bandgap material based power semiconductor devices and ESD reliability in advanced and beyond CMOS nodes. He had held visiting positions in Infineon Technologies, Munich, Germany from April 2008 to October 2008 and again in May 2010 to July 2010. He worked for Infineon Technologies, East Fishkill, NY, USA; IBM Microelectronics, Burlington, VT, USA; Intel Mobile Communications, Hopewell Junction, NY, USA; and Intel Corp., Mobile and Communications Group, Munich, Germany between 2010 and 2013. He joined Indian Institute of Science as a faculty member in year 2013. More details about his group and work can be found at:
    • James Stathis
       - Science and Technology Operations and Strategy
      IEEE Fellow
      Thomas J. Watson Research Center
      Yorktown Heights, NY USA
      Jim Stathis has a Ph.D. in Physics from the Massachusetts Institute of Technology. He is currently head of operations and strategy for science and technology at the IBM T. J. Watson Research Center. He is the author or coauthor of more than 150 research papers and over 80 invited talks on defects, wearout and breakdown. He was the Technical Program Chair for IRPS 2009 and General Chair for IRPS 2011. He was an Associate Editor of the journal Microelectronics Reliability from 2005-2017, and is a Fellow of the American Physical Society and an IEEE Fellow.
    • Suresh Uppal
    • Chadwin D. Young
       - Assistant Professor
      University of Texas at Dallas
      Materials Science and Engineering and Electrical Engineering
      Richardson, TX 75080
      Chadwin D. Young received his B.S. degree in Electrical Engineering from the Univ. of Texas at Austin in 1996 and his M.S. and Ph.D. in EE from the North Carolina State University in 1998 and 2004, respectively. In 2001, he joined SEMATECH where he completed his dissertation research on high-k gate stacks and continued this research at SEMATECH working up to Senior Member of the Technical Staff on electrical characterization and reliability methodologies for the evaluation of high-k gate stacks on current and future device architectures. He joined (09/12) the Materials Science and Engineering Department at the University of Texas at Dallas as an Assistant Professor where his research focus is on electrical characterization and reliability methodologies for the evaluation of future materials and devices. He has authored or co-authored 250+ journal and conference papers. He has served: on the management or technical program committees of IIRW, IRPS, SISC, IEDM, WoDiM; as Guest Editor for IEEE Transactions on Device and Materials Reliability; and as a peer reviewer for several journals. He is currently a Senior Member of IEEE.