Compact Modeling Committee

Talk titles:

·        Modeling and Simulation of Negative Capacitance Transistors

·        Compact Modeling of GaN HEMTs using industry standard ASM-HEMT model

·        Physics and Modeling of FinFET and Nanosheet Transistors

·        Analog and RF Modeling in BSIM-BULK model

·        Physics and Modeling of FDSOI Transistors

Yogesh Singh Chauhan is an associate professor at Indian Institute of Technology Kanpur (IITK), India. He was with Semiconductor Research & Development Center at IBM Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; University of California Berkeley during 2010-2012; and ST Microelectronics during 2003-2004. He is the developer of several industry standard models: ASM-GaN-HEMT model, BSIM-BULK model (formerly BSIM6), BSIM-CMG model and BSIM-IMG model. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs. His research interests are characterization, modeling, and simulation of semiconductor devices.

            He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the member of IEEE-EDS Compact Modeling Committee and fellow of Indian National Young Academy of Science (INYAS). He is the founding chairperson of IEEE Electron Devices Society U.P. chapter and Vice-chairperson of IEEE U.P. section. He has published more than 200 papers in international journals and conferences.

            He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award, Humboldt fellowship and Swarnajayanti fellowship in 2018. He has served in the technical program committees of IEEE International Electron Devices Meeting (IEDM), IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), IEEE European Solid-State Device Research Conference (ESSDERC), IEEE Electron Devices Technology and Manufacturing (EDTM), and IEEE International Conference on VLSI Design and International Conference on Embedded Systems.

Lixin Ge is a principal engineer at Qualcomm Inc., San Diego, California. He received his M.S. degree from National University of Singapore in 1997 and Ph.D. degree from University of Florida, Gainesville in 2002, both from electrical engineering. His research was focused on the modeling and design of double gate and SOI CMOS devices and circuits, emerging technologies and devices including FinFETs and gate-all-around MOSFETs, and design-technology co-optimization. Dr. Ge joined Qualcomm in 2008 as a SPICE modeling expert, and has been instrumental in supporting over 30 product designs which are now in volume production. He is currently leading 7nm/5nm FinFET SPICE modeling projects, and design-technology co-optimization for next generation mobile chip. He received Qualcomm Upendra Patel Achievement Award for the outstanding contributions towards 28nm technology commercialization and for enabling the first Snapdragon chipset MSM8960 commercial launches in 2012, and Qualcomm Super Qualstar Award in recognition of the contribution for going above and beyond in supporting 10nm technology in 2017. Prior to joining Qualcomm, Lixin held various positions at Freescale Semiconductor/Motorola, Texas Instruments, and Chartered Semiconductor (now Globalfoundries). He is a senior member of IEEE, and had authored and co-authored over 30 publications, and has 16 issued and 21 pending patents.

Genquan Han received B.S. degree in material science and engineering from Tsinghua University, Beijing, in 2003, and Ph.D. degree in microelectronic and solid-State electronics from Institute of Semiconductors, Chinese Academy of Sciences in 2008. From 2008 to 2013, he was a Research Fellow with Silicon Nano Device Laboratory (SNDL), National University of Singapore. His research focused on design and fabrication of tunneling transistors and high mobility channel MOSFETs.  In 2013, he joined the college of optoelectronic engineering, Chongqing University. Since May 2015, he joined the school of microelectronics, Xidian University, as a Professor. His current research interests include high mobility channel transistors, steep slope devices, such as negative capacitance FETs, Ga₂O₃ wide bandgap devices, and group-IV photonics.

Prof. Lan Wei received her B.S. in Microelectronics from Peking University, China (2001), M.S and Ph. D. in Electrical Engineering from Stanford University, USA (2007 and 2010, respectively). She worked as a Postdoc Associate in MIT from 2010-2012 and as a Member of Technical Staff with Altera Corporation from 2012-2014. She joined University of Waterloo, Canada, in 2014, where she is currently an Associate Professor.

Prof. Wei has intensive experience in device physics-based compact modeling including silicon and GaN technologies, device-circuit interactive design and optimization, integrated nanoelectronic systems with low-dimensional materials, cryogenic CMOS device modeling and circuit design for quantum computing. She was listed as one of the key contributors to the Process Integration, Devices, and Structures Chapter (PIDS) of International Technology Roadmap for Semiconductors (ITRS) 2009 Edition. She is the co-developer of the MIT Virtual Source GaN HEMT (MVSG) Compact Model, which is an Industry Standard approved and supported by the Compact Model Coalition for GaN HEMT compact model.

She has authored/co-authored more than 100 peered reviewed publications and served on the technical program committees including IEDM, ICCAD, DATE, ISQED, and BCICTS etc.