CMOS Device Scaling - Past, Present, and Future Abstract

CMOS technology ushered in the silicon VLSI era over thirty years ago. This tutorial reviews the history of CMOS devices and projects their future prospects. For any given technology node, CMOS performance is limited by the shortest channel length that can be made while maintaining the integrity of transistor action. The development of the MOSFET scale length theory will be tracked from the 1970s to the present, as it evolves from the one-region model for bulk MOSFETs, to the two-region model for dealing with thick, high-k gate dielectrics, then to the three-region model for multiple-gate MOSFETs such as FinFETs. It gives powerful guidelines that, along with quantum mechanical considerations, allow the projection of scaling limits for bulk, SOI, double-gate, and nanowire MOSFETs.