Memory – the N3XT Frontier Abstract

Computer architecture is going to change in the coming decade because today’s architecture has severe limitations in energy efficiency and latency for memory access.

At the same time, new types of non-volatile memory have emerged that can easily be integrated on-chip with the microprocessor cores. Some of them can be programmed and read quickly; others can have very high data storage density. Importantly, all of these memories are free from the limitations of Flash — that is, low endurance, need for high voltage supply, slow write speed and cumbersome erase procedure. Fine-grain, monolithic 3D integration of massive memory with logic will be the next frontier that will provide more than 1,000× improvement in energy efficiency of computing systems [1]. 

I will give an overview [2] of the “new” memory technologies that are being explored currently in industry and in academia: magnetic memory, resistive switching metal oxide memory [3], conductive bridge memory, phase change memory [4]. I will go over the fabrication process, essential device characteristics, and potential applications. To facilitate a connection with circuit designers, a compact model for RRAM has been developed and made available to the public [5]. I will describe our efforts to explore device size scaling below 10 nm as well as 3D stacking of RRAM and the use of nanomaterials such as graphene in RRAM and PCM devices.

Work supported in part by STARnet SONIC, IARPA, SRC/GRC, NSF, and member companies of the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI) and Stanford SystemX Alliance.


[1] M. M. Sabry Aly et al., IEEE Computer, p. 24 (2015)

[2] H.-S. P. Wong, S. Salahuddin, Nature Nanotechnology, p. 191 (2015)

[3] H.-S. P. Wong et al., Proc. IEEE, p. 1951 (2012)

[4] H.-S. P. Wong et al., Proc. IEEE, p. 2201 (2010)

[5] doi:10.4231/D37H1DN48

H.-S. Philip Wong

Department of Electrical Engineering and Stanford SystemX Alliance, Stanford University

Stanford, California 94305