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Editor-in-Chief and Editors
Edmundo A. Gutierrez-D. - Solid State Device Phenomena; Emerging Technologies and Devices Dr. Edmundo A. Gutiérrez-D. Got his PhD in 1993 from the Catholic University of Leuven, Belgium with the thesis entitled “Electrical performance of submicron CMOS technologies from 300 K to 4.2 K”. From 1989 to 1993, while working for his PhD, served as a research assistant at the Interuniversity Microelectronics Center (IMEC) in Leuven, Belgium. In 1996 was guest Professor at Simon Fraser University, Vancouver, Canada. In 1996 spent two months as an invited lecturer at the Sao Paulo University, Brazil. In 2000 acted as Design Manager of the Motorola Mexico Center for Semiconductor Technology. In 2002 was invited lecturer at the Technical University of Vienna, Austria. In 2005 joined the Intel Mexico Research Center as technical Director. Currently he holds a Professor position at the National Institute for Astrophysics, Optics and Electronics (INAOE), in Puebla, Mexico. Prof. Gutiérrez-D. is an IEEE senior member since 2008. Professor Gutiérrez-D. has published over 100 scientific publications and conferences in the field of semiconductor device physics, has supervised 5 M.Sc. and 10 Ph.D. thesis, and is author of the book “Low Temperature Electronics, Physics, Devices, Circuits and Applications” published by Academic Press in 2000. Prof. Gutiérrez-D. is member of the Mexico National System of Researchers and technical reviewer for the Mexico National Council for Science and Technology (CONACyT).T-DMR Editor-in-Chief
for Astrophysics, Mexico
T-DMR Editors
Gennadi Bersuker - Gate Dielectrics, Transistors

Austin, TX, USA
Gennadi Bersuker completed his M.S. and Ph.D. in Physics at the Leningrad State University and Kishinev State University, respectively. After graduation, he joined Moldavian Academy of Sciences, and then worked at Leiden University and the University of Texas at Austin. Since 1994, he has been working at SEMATECH on electrical characterization of Cu/low-k interconnect, high-k gate stacks, advanced memory, and CMOS process development. He has been involved in organizing, chairing, or serving as a committee member in a number of technical conferences, including IRW, IRPS, IEDM, ULSI-TFT, ISAGST, LEC, NGCM, APS. He is a SEMATECH Fellow and has published over 200 papers on the electronic properties of dielectrics and semiconductor processing and reliability.
Kin P. Cheung - Gate-Dielectrics, Transistors, Processing

Dr. Kin P. Cheung, obtained Ph.D. degree in physical chemistry from the New York University in 1983. From 83 to 85 he was a post doc at Bell Laboratories during which he pioneered Terahertz Spectroscopy. From 1985 to 2001 he was a member of technical staff in Bell Laboratories at Murray Hill. From 2001 to 2006, He was an associate professor at Rutgers University. He is currently a project leader at the National Institute of Standards & Technology, Semiconductor Electronics Division. Dr. Cheung published over 140 refereed journal and conference papers. He authored a book on plasma charging damage, a book chapter and edited three conference proceedings. He served in the committee of a number of international conferences and has given tutorial in 10 international conferences. His area of interest is VLSI technology and devices.
Isodiana Crupi

Palermo, Italy
Isodiana Crupi is Associate Professor at the Department of Engineering at the University of Palermo. She received the M.Sc. degree in Electronic Engineering from the University of Messina in 1999 and the Ph.D. degree in Materials Science from the University of Catania in 2003. From 2004 to 2015 she has been Research Scientist at the National Research Council (CNR-IMM) in Catania. Since 1998, she has been a frequent scientific visitor at IMEC, Leuven (Belgium) collaborating with the CMOS Reliability, FLASH Memory and Solar Cell groups and at the Czech Academy of Sciences, Praha, Czech Rep. Her main research interests include the synthesis and characterization of innovative materials for photovoltaic applications, electrical characterization of advanced semiconductor devices for micro- and optoelectronics and the development of silicon nanocrystals devices for memory applications. Prof. Crupi has authored and coauthored more than 90 papers published on ISI journals and international conference proceedings which have been cited about 1700 times (h-index of 25). She is coinventor of one U.S. Patent, participant of several national and EU research projects and supervisor of several Master and PhD theses. She serves as referee for outstanding international scientific journals and co-organized various symposia at the European Materials Research Society (E-MRS). She is a technical program committee member of the IEEE International Electron Devices Meeting (IEDM) in 2019 and, since 2012, of the European Solid-State Device Conference (ESSDERC). She received the "Young Scientist Award" at the E-MRS (2003) and the "Premio per Dottori di Ricerca" from the Accademia Gioenia (2004).
Abhisek Dixit - Modelling and Characterization of Reliability for Si- and GaN-based Devices

Indian Institute of Technology Delhi
Dr. Abhisek Dixit is currently an Associate Professor in the Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, INDIA. Other positions he held prior to this include Assistant Professor of Electrical Engineering at IIT Delhi and Advisory Research Engineer at IBM SRDC. Dr. Dixit received his PhD from K. U. Leuven/IMEC BELGIUM in 2007 and MTech from IIT Bombay, INDIA in 2002. He has worked on fabrication, characterization, compact and TCAD modeling of devices and circuits on various 300 and 200-mm technologies, including bulk Si, PD and FD-SOI, BiCMOS. Although his modeling and characterization work spans range of technology nodes all the way from 10-nm up to 0.35-micron, in his early career he focused on SOI- FinFET device-technology integration at 45, 32, 14-nm nodes. His current research interests include CMOS reliability including hot-carrier degradation and radiation hardness, pulsed/RF characterization and modeling of logic devices, and device scaling of SOI, nanowire, nanosheet, and negative capacitance-FETs beyond 7-nm nodes. Dr. Dixit has more than 60 publications and 4 patents in FinFET and related technologies and he is a senior member of IEEE since 2013.
Lecture Topics:
- CMOS logic device scaling
- Negative Capacitance FETs
- Gamma and Heavy Ion Irradiation Effects in CMOS
- CMOS-RF models
- CMOS Thermal Effects and Modeling
Oscar Huerta - Globalfoundries Inc Malta

Ming-Dou Ker - ESD, System Reliability

Electronics Engineering
Pey Kin Leong - Dielectrics

School of Electrical and Electronic Eng.
Dr. Pey Kin Leong received his Bachelor of Engineering (1989) and Ph.D (1994) in Electrical Engineering from the National University of Singapore. He has held various research positions in the Institute of Microelectronics, Chartered Semiconductor Manufacturing, Agilent Technologies and National University of Singapore. He is currently a Professor, Head of the Microelectronics Division, Director of Nanyang Nanofabrication Center and Director of the Microelectronic Center in the School of Electrical & Electronics Engineering, Nanyang Technological University, Singapore and holds a concurrent Fellowship appointment in the Singapore-MIT Alliance (SMA). Dr. Pey is a senior member of IEEE and an IEEE EDS Distinguished Lecturer, and has been the organizing committee member of IPFA since 1995. He was the General Chair of IPFA2001, Singapore and the co-General Chair of IPFA2004, Hsinchu, Taiwan. KL Pey was the Guest Editor of IEEE Transactions on Devices and Materials Reliability in 2003-05, and the Chair of the Singapore IEEE REL/CPMT/ED Chapter in 2004/05 and 2009 and served on the 2006/07/08 IRPS technical subcommittee, IPFA’02 to IPFA’06, IPFA’08 and IPFA’09 technical subcommittee and 2007 IEDM CMOS & Interconnect Reliability and 2008 IEDM Characterization, Reliability and Yield sub-committee. Dr. Pey has published more than 145 international refereed publications and 150 technical papers at international meetings/conferences and holds 33 US patents. Dr. Pey's research focuses are on pulsed laser annealing for channel engineering for nano-scale CMOS, advanced alloy silicide for nanostructures and nanodevices and transistor reliability in dielectric breakdown and advanced interconnects. Dr. Pey pioneers in using physical analysis techniques such as TEM and EELS in the study of breakdown mechanisms in ultrathin SiON and high-k gate stack.
Karumbu Meyyappan - Modeling, Board & Package/Substrate Assembly, Reliability Areas

Dr. Karumbu Meyyappan is a senior staff engineer at Intel Corporation in Assembly & Test Technology Development division. In his current role, he leads strategic programs related to the areas of test and next generation interconnect solutions. Through his 16 years at Intel he has covered wide areas of reliability physics spanning Silicon back end to board level interconnects, design, predictive modeling, and development of reliability test methods including knowledge based qualification methods. He has published over 30 peer reviewed articles and has 5 patents. He is also a recipient of the Erle Shobert Prize Paper award in 2014. He received his PhD from University of Maryland College Park, MD, USA
C. Glenn Shirley - Reliability Theory, Packaging

Dr. C. Glenn Shirley is an adjunct faculty member with the Integrated Circuit Design and Test Laboratory in the ECE department at Portland State University (Oregon). He retired in 2007 after 23 years at Intel, anda prior 10 years at Motorola, U.S. Steel and Carnegie-Mellon University (post-doc). At Intel Dr. Shirley worked and published on package reliability, moisture reliability of silicon, accelerated moisture test hardware (HAST), and industry standards. He also led the development of Intel’s burn-in methodology, founded a manufacturing test technology development Q&R group, and started a Q&R statistical modeling group. Subsequently he co-directed, as Intel’s Q&R Systems Architect, a department reponsible for Intel’s quality systems. Dr. Shirley’s current interests include yield/quality/reliabilitystatistical modeling of manufacturing test. Dr. Shirley holds a PhD in Physics from Arizona State University, and an MSc in Physics from the University of Melbourne (Australia).
Albert Z.H. Wang - Fellow - IEEE

Dept. of Electrical and Computer Engineering
Albert Wang is a Professor of Electrical and Computer Engineering at the University of California, Riverside, California, USA. He currently serves as a Program Director of National Science Foundation, USA. His research interests cover semiconductor devices, AMS/RF ICs, integrated design-for-reliability, 3D heterogeneous devices and integration, emerging nano devices and circuits. He authored 1 book and more than 280 papers, and holds 16 US patents. He was President for IEEE Electron Devices Society (2014-2015). His editorial services include IEEE Electron Device Letters, IEEE Transactions on Circuits and Systems I, IEEE Transactions on Circuits and Systems II, IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices and IET Journal of Engineering. He has been an IEEE Distinguished Lecturer for IEEE Electron Devices Society, IEEE Solid-State Circuits Society and IEEE Circuits and Systems Society. He served on ITRS committee, IEEE 5G Initiative committee and IEEE Fellow Committee. He was General Chair (2016) for IEEE RFIC Symposium and is General Chair (2021) for IEEE EDTM conference. He is Fellow of National Academy of Inventors, Fellow of IEEE Fellow and Fellow of AAAS.
Mustafa Berke Yelten - Associate Professor

Mustafa Berke Yelten (Senior Member, IEEE, 2018) received the B.Sc. degree (High Hons.) in electrical engineering from Boğaziçi University, Istanbul, Turkey, in 2006, and the M.Sc. and Ph.D. degrees in electrical engineering from North Carolina State University, Raleigh, NC, USA, in 2008 and 2011, respectively. He was a Quality-Reliability Research Engineer with Intel Corporation, Hillsboro, OR, USA, from 2011 to 2015. Since 2015, he has been with the Electronics and Communications Engineering Department, Istanbul Technical University, Istanbul, where he is currently an Associate Professor. His research interests include the design, optimization, and modeling of nanoscale transistors and the design of analog/RF integrated circuits with a focus on reliability and operation under extreme conditions (cryogenic temperatures, high ionizing radiation, etc.).
- Publications
- EDS Newsletter
- EDS 50th Anniversary Booklet
- IEEE Guidelines for Authors
- Electron Device Letters
- Journal of the Electron Devices Society
- Transactions on Electron Devices
- Journal of Microelectromechanical Systems
- Journal of Photovoltaics
- Transactions on Device and Materials Reliability
- Transactions on Semiconductor Manufacturing
- Editorials for Authors and Reviewers
- Publication Representatives
- Publication Editors in Chief
- Publications Committee
- Journal on Flexible Electronics
- Journal of Lightwave Technology
- Journal on Exploratory Solid-State Computational Devices and Circuits