Editor-in-Chief and Editors

Jesus A. del Alamo is the Director of the Microsystems Technology Laboratories at Massachusetts Institute of Technology. He obtained a Telecommunications Engineer degree from the Polytechnic University of Madrid and MS and PhD degrees in Electrical Engineering from Stanford University. From 1985 to 1988 he was with Nippon Telegraph and Telephone LSI Laboratories in Japan and since 1988 he has been with the Department of Electrical Engineering and Computer Science of Massachusetts Institute of Technology where he is the Donner Professor. His current research interests are centered on nanoelectronics based on compound semiconductors. Prof. del Alamo was an NSF Presidential Young Investigator. He is a member of the Royal Spanish Academy of Engineering and Fellow of the Institute of Electrical and Electronics Engineers and the American Physical Society. He is the recipient of the Intel Outstanding Researcher Award in Emerging Research Devices, the SRC Technical Excellence Award, and the IEEE Electron Devices Society Education Award. He served as editor of IEEE Electron Device Letters for 9 years.

Biography: Albert Chin received Ph.D. from University of Michigan, Ann Arbor, in 1989 and B.S. from National Tsing Hua University in 1982. He was with AT&T Bell Labs, General Electric E-Lab, and Texas Instruments SPDC. He has been a professor, vice executive officer of diamond project and deputy director of National Chiao Tung University, and a visiting Professor at National University of Singapore. He is a pioneer on low DC-power high-κ CMOS, high-κ Flash memory, high mobility Ge-On-Insulator, low AC-power 3D IC, high power asymmetric-MOSFET, Si fs/THz devices, and resonant-cavity photo-detector. He co-authored >500 papers and 7 “Highly Cited Papers” (top 1% citation). His high-κ CMOS, GeOI, Flash memory, and RF devices were also cited by ITRS www.itrs.net Dr. Chin has served as Subcommittee Chair and Asian Arrangements Chair of IEDM Executive Committee, Editor of IEEE Electron Device Letters, Guest Editor & Editor-in-Chief of IEEE JEDS Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices, and IEEE EDS Technical Committee Chairs on both Electronic Materials and Compound Semiconductor Devices & Circuits. He is an IEEE Fellow, Optical Society of America Fellow, and Asia-Pacific Academy of Materials Academician.

 

Lecture Topics:

- Device-Circuit Co-design for RF & AI Memory
- Monolithic Three-Dimensional IC Devices for Brain-Mimicking IC Hardware
- Ultra-low power & energy-efficient green electronic devices

Brian Doyle received his B.Sc. degree from Trinity College Dublin (Ireland), and his M.Sc. & Ph.D. degrees from the University of London, Chelsea College (Great Britain). Following a post-doctorate position at the University of London, he worked at Bull S.A. in France on low temperature operation of nMOS circuits, and then transistor reliability before moving to Massachusetts to work for Digital Equipment Corporation on reliability of MOS devices and gate oxide development. Following six years at DEC, he moved to Intel in 1994 where he worked initially investigating the transistor gate stack, then developing scaled transistors, and now examining embedded memories. Dr Doyle is the author of more than 100 papers in internationally recognized scientific journals as well as a book chapter in ULSI Devices. He has over 200 US and international patents. He has worked in various professional capacities: he has been on the technical committee (reliability) of the International Technology Roadmap for Silicon (ITRS). He has worked at various levels on the technical committees of the International Electron Device Meeting (IEDM), the International Silicon-On-Insulator conference and the Device Research Conference (DRC). He was previously editor of the IEEE Electron Device Letters in the 1990’s. Dr Doyle received a SEMI Award for Process and Technology Integration Breakthrough in High-K/Metal Gate in 2013, as well as a further SEMI Award for North America for the implementation of bulk CMOS finFET production in 2015. He also received two Intel Achievement Awards (Intel’s highest award) for work on transistor scaling and for developing Tri-Gate transistors, and as well as numerous internal Intel Divisional Awards.

Harald Gossner (M ‘07, SM ‘11) is Senior Principal Engineer at Intel. He received his degree in physics (Dipl. Phys.) from the Ludwig-Maximilians-University, Munich in 1990 and his Ph. D. in electrical engineering from the Universität der Bundeswehr, Munich in 1995. For 15 years he worked on the development of ESD protection concepts with Siemens and Infineon Technologies, heading the ESD development team of Infineon Technologies. In 2010 he has joined Intel overseeing the development of robust mobile systems.

Harald Gossner has authored and co-authored more than 130 technical papers and two books in the field of ESD and device physics. He holds 60 patents on the same topic. He received several best paper awards of EOSESD Symposium and has been the recipient of the 2015 Outstanding Contribution Award of ESD association. He is lecturer of tutorials at ESREF, IRPS and EOSESD symposium and has served in technical program committees of IEDM, EOSESD Symposium and International ESD Workshop. In 2006 he became cofounder and co-chair of the Industry Council on ESD Target Levels. Since 2012 he is also member of the board of directors of ESD Association and currently holds the position of a vice president of the organization.

Professor Steve Hall has interests spanning materials characterisation, device physics & innovative device design and gate level circuits. He has about 250 conference and journal papers in these areas including novel measurements and contributions to the understanding of MOS related interfaces and materials quality. He successfully designed and built novel MOS and bipolar devices in silicon for about 20 years. More recently, his work encompasses high permittivity dielectrics, conducting oxides, rectennas for energy scavenging and biologically inspired device/circuit concepts. He was Technical Programme Chair of ESSDERC 2008, guest editor of selected papers in Solid-State Electronics and currently sits on the Steering Committee of ESSDERC/ESSCIRC. He serves on the programme committees of ESSDERC and INFOS, for which he was vice-Chair in 2009 and is a member of the Steering Committee from 2009. He was co-organiser of a NATO Advanced Workshop in 2007 and co-editor of proceedings. He was active in the EU Networks of Excellence FP6 SINANO, FP7 NANOSIL and managed WP4 in the EU FP5 project SIGMOS. He participated in the major FP6 Integrated Project PULLNANO and is a founder member of the European SINANO Institute, where he chairs the General Assembly. He serves on the Editorial Advisory Board of Solid-State Electronics. He is a Fellow of the IET, a Chartered Engineer and a Senior Member of IEEE. He was Head of his University Department from 2001 to 2009 and is currently the Director of Research.

Steven J. Koester (M’96–SM’02) was born in Defiance, Ohio, in 1966. He received the B.S.E.E. and M.S.E.E. degrees from the University of Notre Dame in 1989 and 1991, respectively. He received his Ph.D. in 1995 from the University of California, Santa Barbara where he performed research on quantum devices in the InAs/AlSb heterostructure system. In 1995, he joined the IBM T. J. Watson Research Center, in Yorktown Heights, New York, as a postdoctoral researcher. From 1997 to 2006 he was a research staff member at IBM and performed research on a wide variety of SiGe devices including strained Si/SiGe MODFETs, MOSFETs and high-speed photodetectors. From 2006-2010 he served as manager of Exploratory Technology at IBM Research where his team investigated novel devices and 3D integration solutions for post 22-nm-node CMOS technology. Since 2010, he has been a Professor of Electrical and Computer Engineering at the University of Minnesota in Minneapolis, Minnesota where his research focuses on nanostructured electronic and photonic devices. Dr. Koester has authored or co-authored over 150 technical publications and conference presentations, and holds 32 United States patents.

Kelin J. Kuhn (M’78–SM’04-F’11) received the B.S. degree in electrical engineering from the University of Washington, Seattle, in 1980 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Palo Alto, CA, in 1985. Prior to 1997 she was a tenured Associate Professor with the Department of Electrical and Computer Engineering, University of Washington. In 1997, she joined Intel Corporation, Hillsboro, OR, working on the Intel 0.35-μm process technology and was involved in Intel manufacturing process technology development for the 0.35-μm, 130-nm, 90-nm, 45-nm, 22-nm, 14-nm, and 7nm technology nodes. She retired from Intel in 2014 with the title of Intel Fellow and Director of Advanced Device Technology in the Components Research Group of Intel Corporation. She is presently the Mary Shepard B. Upson Visiting Professor in the Department of Materials Science and Engineering at Cornell University. She is the author of more than 100 technical papers in electronics and photonics, as well as the author of the textbook Laser Engineering (Prentice-Hall, 1997) and an editor (in partnership with Prof. T.J.K. Liu) of the book CMOS and Beyond: Logic Switches for Terascale Integrated Circuits (Cambridge, 2015). Dr. Kuhn is an IEEE Fellow, recipient of the IEEE Frederik Philips Award (2016), the IEEE Paul Rappaport Award (2013), and two Intel Achievement Awards (Intel’s highest technical award) one 2006 (for HiK-MG) and one in 2008 (for key contributions to Intel’s 22nm TriGate technology). She is also a past recipient of the NSF Presidential Young Investigator award (1991-7).

Bengt Gunnar Malm (M’98 - SM’10) was born in Stockholm, Sweden, in 1972. He received the M.S. degree in engineering physics and radiation science from Uppsala University, Uppsala, Sweden, in 1997. He was also an intern at ABB AB, Sweden, in 1996. In 1997 he joined the Royal Institute of Technology (KTH) Stockholm, where his thesis work focused on high-speed silicon-germanium (SiGe) transistors. He received the Ph.D. degree in solid-state electronics in 2002. In 2011 he received the Docent degree also from KTH. Currently, he is an Associate Professor in integrated devices and circuits, and serves as director of undergraduate studies at the Department of Electronics, KTH. His research interests include semiconductor and spintronic device physics, characterization with emphasis on noise, fluctuations and variability, and also TCAD modeling. His recent work includes silicon-carbide (SiC) integrated circuits for extreme environments and phase noise in microwave spintronic oscillators. He has been the main advisor for 2 PhD students and has published or co-authored more than 90 scientific papers in international journals and conferences. He has coauthored 2 book chapters, a number of invited conference papers and tutorials, and has one granted US patent. Dr. Malm is a member of the ESSDERC TPC and co-chair for 2011 event in Helsinki. He was an organizer of ISTDM 2010 and ULIS 2014, and the 2012 general chair for the biannual GigaHertz Symposium and Swedish Radio and Microwave Days. He has an active interest in sustainability issues and served on the KTH Sustainability Council (KTH-S) 2011-2015.

Hidenori Mimura received B.E, M.E and Ph.D degrees in electronics from Shizuoka University, 1979, 1981 and 1987, respectively. He joined Nippon Steel Corporation in 1987, and the ATR Optical Radio Communications Research Laboratories in 1994. From 1996 to 2003, he was an associate professor in the Research Institute of Electrical Communications, Tohoku University. In 2003 he moved to the Research Institute of Electronics, Shizuoka University, and since then he has been a professor in the Research Institute of Electronics, Shizuoka University. Since 2006 he has been a director of the Research Institute of Electronics, Shizuoka University. He is an honorary professor of St. Petersburg State Institute of Technology, and an adjunct professor of University Indonesia. He has published more than 210 papers. He is a leading researcher of Shizuoka University. He has been engaged in vacuum nanoelectronics, and imaging devices. Prof. Mimura is a member of the Japan Society of Applied Physics, the Institute of Electronic, Information and Communication Engineering, the Institute of Image Information and Television Engineering, the Vacuum Society of Japan, the Society for Information Display and the IEEE Electron Devices Society.

Victor Moroz received M.S. degree in Electrical Engineering from Novosibirsk Technical University and Ph.D. degree in Applied Physics from the University of Nizhny Novgorod. After engaging in technology development at several semiconductor manufacturing companies and teaching at the University of Nizhny Novgorod, Dr. Moroz joined Technology Modeling Associates in 1995, which later became a part of Synopsys. Currently Dr. Moroz is a Synopsys Fellow, engaged in a variety of projects on modeling FinFETs, gate-all-around nano-wires, stress engineering, 3D ICs, transistor scaling, Middle-Of-Line and Back-End-Of-Line RC, solar cell design, innovative patterning, random and systematic variability, junction leakage, non-Si transistors, and atomistic effects in layer growth and doping. Several facets of this activity are reflected in three book chapters and over 100 technical papers, invited presentations, and patents. He has been involved in technical committees at ITRS, IEDM, SISPAD, DFM&Y, ECS, IRPS, and ESSDERC.

Chandra Mouli is with Micron Technology Inc., Boise, ID, USA. He is currently Director of Device Technology with responsibilities in the area of advanced device characterization, reliability analysis, test structure design/layout, process & device modeling for all technologies under development in R&D. He received his undergraduate degree in Physics and MSEE from the Indian Institute of Science (IISc), Bangalore, India and Ph.D (EE) from the University of Texas at Austin. He was with Texas Instruments for couple of years before joining UT/Austin. His interests include semiconductor devices and process technology for advanced memory, opto-electronic devices, exploratory research in the area of new materials and device structures. He has more than hundred issued patents and several pending in various areas of semiconductor devices and process – in advanced memory, novel devices and image sensor technology. He has served in the technical committees for various conferences, including IEDM, IRPS and SISPAD. He has also served in the review committees for NSF and SRC. He is currently a member of the scientific advisory board in SRC’s focus center programs and is a member of the ITRS technical working group.

Azad Naeemi (S’99-M’04-SM’04) received the B.S. degree in electrical engineering from Sharif University, Tehran, Iran, in 1994, and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology (Georgia Tech), Atlanta, in 2001 and 2003, respectively. He worked as a research engineer with the Microelectronics Research Center, Georgia Tech, from 2003 to 2008. In 2008, he joined the School of Electrical and Computer Engineering faculty at Georgia Tech, where he is currently an associate professor. His research crosses the boundaries of materials, devices, circuits and systems, investigating integrated circuits based on conventional and emerging nanoelectronic and spintronic devices and interconnects. As silicon field-effect transistors and copper/low k interconnects approach their scaling limits, this research aims at finding evolutionary and revolutionary approaches to sustain the growth of the computing power of microchips. Dr. Naeemi serves as the leader of the beyond-CMOS benchmarking research at the Semiconductor Research Corporation (SRC) Nanoelectronics Research Initiative (NRI) and the Semiconductor Technology Advanced Research Network (STARnet). Dr. Naeemi is the recipient of the IEEE Electron Devices Society (EDS) Paul Rappaport Award for the best paper that has appeared in IEEE Transactions on Electron Devices during 2007. He has also received an NSF CAREER Award, an SRC Inventor Recognition Award, and several best paper awards at international conferences. Dr. Naeemi is a recipient of Richard M. Bass/Eta Kappa Nu Outstanding Teacher Award determined by the vote of the Georgia Tech ECE senior class.

Lis K. Nanver (M’80) received a masters degree in physics from the University of Aarhus, Denmark, in 1979, and a docteur ingenieur degree in physics applied to telecommunications from the Ecole Nationale Supérieure des Télécommunications (ENST), Paris, France, in 1982, on the subject of charge-coupled device simulations. She received a Ph.D. degree in electrical engineering from Delft University of Technology, The Netherlands, in 1987. In her doctoral work she developed a medium frequency BiFET IC-process and made it available to designer groups. In 1987 she continued her research on silicon devices and integration processes in DIMES, TU Delft, from 2001-2015 as professor heading the Silicon Device Integration Group. Mainly in cooperation with either RF/microwave or smart sensor IC designer groups she developed several new processing techniques. Her silicon-on-glass substrate-transfer process allowed true two-sided device contacting and was a basis for investigations leading to a better understanding of the electrothermal behavior of bipolar transistors. She has pioneered several ultrashallow diode technologies involving techniques such as laser annealing, Al-mediated solid-phase epitaxy and chemical-vapor deposition (CVD). The research on pure-dopant CVD processes for creating extremely shallow diodes (PureB for Si and PureGaB for Ge devices) has resulted in several leading-edge applications such as high-linearity silicon-on-glass varactor diodes, Si photodiode detectors for low penetration-depth beams and low-leakage Ge-on-Si photodiodes. Prof. Nanver is at present continuing her research as guest professor at University Twente, Enschede, The Netherlands and Aalborg University, Aalborg, Denmark. She has published more than 250 journal and conference articles, has authored two book chapters, and has been awarded 4 patents. Prof. Nanver has served on the committees of BCTM and ESSDERC. The work of her group has received prizes including the 2010 IEDM Roger Haken Award and the 2011 I2MTC Best Paper Award.

Tomás Palacios is a Professor in the Department of Electrical Engineering and Computer Science at MIT. He received his PhD from the University of California - Santa Barbara in 2006, and his undergraduate degree in Telecommunication Engineering from the Universidad Politécnica de Madrid (Spain). His current research focuses on demonstrating new electronic devices and applications for novel semiconductor materials such as graphene and gallium nitride. His work has been recognized with multiple awards including the Presidential Early Career Award for Scientists and Engineers, the IEEE George Smith Award, and the NSF, ONR, and DARPA Young Faculty Awards, among many others. Prof. Palacios has authored more than 300 contributions in international journals and conferences, 10 of which have received a best-paper award, as well as 5 book chapters and more than 30 patents. Prof. Palacios is the founder and director of the MIT MTL Center for Graphene Devices and 2D Systems, as well as the Chief Advisor and co-founder of Cambridge Electronics, Inc.

Debbie G. Senesky is an Assistant Professor at Stanford University in the Aeronautics and Astronautics Department and by courtesy, the Electrical Engineering Department. She received the B.S. degree (2001) in mechanical engineering from the University of Southern California. She received the M.S. degree (2004) and Ph.D. degree (2007) in mechanical engineering from the University of California, Berkeley. She has also held positions at GE Sensing (formerly known as NovaSensor), GE Global Research Center, and Hewlett Packard. She has served as a subcommittee member (2014, 2015) and the subcommittee chair (2016) of the Sensors, MEMS and BioMEMS (SMB) subcommittee of the IEEE International Electron Devices Meeting (IEDM). Her current research interests include the development of micro- and nano-scale sensors, wide bandgap electronics, and interface materials for operation within extreme harsh environments. She is a recipient of the NASA Early Faculty Career Award and Alfred P. Sloan Foundation Fellowship Award.

Massood Tabib-Azar received M.S. and Ph.D. degrees in electrical engineering from the Rensselaer Polytechnic Institute in 1984 and 1986, respectively. In 1987 he joined the faculty of EECS department at Case Western Reserve University. He was a fellow at NASA during 1992-1992, on Sabbatical at Harvard University during 93-94, and at Yale University during 2000-2001. Massood is a USTAR Professor of ECE at the University of Utah, Electrical and Computer Eng. Department with an adjunct appointment in the Bioengineering Department. His current research interests include nanometrology, molecular electronics, micro-plasma devices, nano-electromechanical computers, novel devices based on solid electrolytes (memristors), sensors and actuators, microfluidics, and quantum computing. His teaching interests include development of courses in the area of electronic device physics and electromagnetics with an emphasis on solving problems and the use of computer-aided instruction tools. He is author of three books, two book chapters, more than 200 journal publications, and numerous conference proceeding articles. He has introduced and chairs many international symposia in his fields of interest. He is in the organizing and technical program committees of many conferences including IEEE Sensors and Transducers. He is currently serving as a Program Director in the Engineering Directorate at the National Science Foundation and is interested in “Injectable Bio Implants”, “Novel Communication Methods with Cells and Implantables”, “Quantum Sensing Methods”, and techniques to increase efficiencies of photo-synthesis for sun-to-fuel conversion devices. Dr. Tabib-Azar is a recipient of the 1991 Lilly Foundation Fellowship and he is a member of the New York Academy of Sciences, IEEE (Electron Devices), APS, AAPT, and Sigma Xi research societies. He has also received more than 14 certificate of appreciation and recognition for his professional activities and a best paper award from Design Automation conference in 2001 for his work on electromagnetic properties of interconnects and defects in ICs, a best paper award from International Conference on Intelligent Robots and Systems in 2004 for his work on Human-Machine Interface, and a best paper award from ISQED for his work on NEMS Processors in 2011.

Aaron Voon-Yew Thean is a Professor of Electrical and Computer Engineering at the National University of Singapore (NUS). He is also a consulting Fellow to IMEC, a Nano-electronic Research Center, based in Belgium. Prior to joining NUS in 2016, Aaron served as IMEC’s Vice President of Logic Technologies and the Director of the Logic Devices Research. At IMEC, he directed the research and development of advanced device technologies ranging from ultra-scaled FinFETs, Nanowire FETs, to III-V/Ge Channels, Tunnel FETs to emerging Beyond CMOS logic nano-device architectures based on Spintronics and 2-D materials. He has been involved in Design and Process Technology Co-optimizations (DTCO) of emerging technologies targeting 7nm, 5nm, and beyond. Before 2011, he was with Qualcomm’s CDMA technologies in San Diego, California, USA. There, he led the Strategic Silicon Technologies Group responsible for new System-On-Chip technology definition for upcoming Qualcomm technologies. From 2007 to 2009, Aaron served as the International Semiconductor Development Alliance (ISDA) FEOL and Device Manager at IBM, where he co-led an eight-company alliance device/process team to develop the 28-nm and 32-nm low-power bulk CMOS technology at IBM East Fishkill, New York. His team developed the Industry’s first foundry-compatible Gate-First High-k Metal-Gate (HKMG) with novel SiGe channel Low-Power bulk CMOS technologies. It enabled some of today’s most successful smart mobile devices in production by the foundry partners. Before IBM, Aaron was a senior staff scientist with Freescale Semiconductor and Motorola’s Advanced Product Research and Development Laboratory (APRDL). He subsequently led the Novel Device Research Group there in Austin, Texas. He performed path-finding research on a variety of advanced semiconductor devices that included Strained-Si-On-Silicon, FinFETs, FDSOI, and Nano-crystal Flash Memory. Aaron graduated from the University of Illinois at Champaign-Urbana, USA, where he received his B.Sc. (Highest Honors & Graduated as Edmund J. James’ Scholar), M.Sc., and Ph.D. degrees in Electrical Engineering. He was awarded the 2001 Gregory Stillman Semiconductor Research Award for his Ph.D. work. He has published over 300 technical papers and holds more than 50 U.S. patents for inventions in the field of advanced electronics. Among his notable recognitions include the 2014 Compound Semiconductor Industry Innovation award for his research group’s break-though III-V FinFET work. In 2013, he was given the Best Collaboration Award from Samsung Electronics Korea for R&D collaborations contributing towards its Semiconductor R&D Center. Aaron received the 2010 Young Alumni Achievement Award from his Alma Mater, University of Illinois, for his contribution to advanced transistor R&D, as well.

Dr. Yifeng Wu received his B.E. degree from Tsinghua University, Beijing in 1985, his M.S. degree in Mechanical Eng. and his Ph.D. degree in Electrical Eng. from the University of California at Santa Barbara in 1994 and 1997, respectively. He served as a lead scientist in GaN microwave and millimeter-wave power devices at WideGap Technology LLC and Cree Inc. for 11 years. He joined Transphorm Inc. in 2008, leading the engineering effort in developing GaN power conversion devices and applications. Since his early research on GaN high-electron-mobility-transistors (HEMTs) as a Ph.D. project in 1995, Dr. Wu has been active at the forefront of GaN power electronics with work from basic device discovery to cutting-edge device designs, from millimeter-wave power HEMTs to kV high-efficiency power switches. He demonstrated the first GaN microwave power transistor [EDL 1996] and multiple times extended the record of the highest power density of a solid-state transistor [EDL 1998, IEDM 1999, EDL 2004, DRC 2006]. He led an engineering team at Transphorm and succeeded in developing industry’s first Jedec-qualified 600V GaN-on-Si power device products [WiPDA 2013]. His team further demonstrated true kV-class GaN transistors exceeding vertical SiC performance, reaching an operation space unprecedented for horizontal devices [TPE 2014]. Dr. Wu holds 75 US patents and has authored significant papers resulting in >6500 citations in Google Scholar. He is a senior member of the IEEE (EDS).